From: Sheldon Lobo Date: Thu, 23 Feb 2017 15:49:37 +0000 (-0800) Subject: opcodes,gas: associate SPARC ASIs with an architecture level. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1e9d41d49f7f0b9e7381e8bf8ce848f8a33b8fde;p=binutils-gdb.git opcodes,gas: associate SPARC ASIs with an architecture level. With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index bf3e038a55a..415237c6946 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2017-02-23 Sheldon Lobo + + Add support for associating SPARC ASIs with an architecture level. + * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. + 2017-02-23 Jan Beulich * testsuite/gas/all/err-sizeof.s: Don't use sums or differences diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index b1651f9a757..030e10d7749 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -36,6 +36,7 @@ #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) static int sparc_ip (char *, const struct sparc_opcode **); +static int parse_sparc_asi (char **, const sparc_asi **); static int parse_keyword_arg (int (*) (const char *), char **, int *); static int parse_const_expr_arg (char **, int *); static int get_expression (char *); @@ -1764,6 +1765,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) int comma = 0; int v9_arg_p; int special_case = SPECIAL_CASE_NONE; + const sparc_asi *sasi = NULL; s = str; if (ISLOWER (*s)) @@ -2969,11 +2971,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) /* Parse an asi. */ if (*s == '#') { - if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) + if (! parse_sparc_asi (&s, &sasi)) { error_message = _(": invalid ASI name"); goto error; } + asi = sasi->value; } else { @@ -3147,8 +3150,18 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) else { /* We have a match. Now see if the architecture is OK. */ + /* String to use in case of architecture warning. */ + const char *msg_str = str; int needed_arch_mask = insn->architecture; - bfd_uint64_t hwcaps + + /* Include the ASI architecture needed as well */ + if (sasi && needed_arch_mask > sasi->architecture) + { + needed_arch_mask = sasi->architecture; + msg_str = sasi->name; + } + + bfd_uint64_t hwcaps = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; #if defined(OBJ_ELF) && !defined(TE_SOLARIS) @@ -3183,7 +3196,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), sparc_opcode_archs[current_architecture].name, sparc_opcode_archs[needed_architecture].name, - str); + msg_str); warn_after_architecture = needed_architecture; } current_architecture = needed_architecture; @@ -3247,6 +3260,35 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn) return special_case; } +static char * +skip_over_keyword (char *q) +{ + for (q = q + (*q == '#' || *q == '%'); + ISALNUM (*q) || *q == '_'; + ++q) + continue; + return q; +} + +static int +parse_sparc_asi (char **input_pointer_p, const sparc_asi **value_p) +{ + const sparc_asi *value; + char c, *p, *q; + + p = *input_pointer_p; + q = skip_over_keyword(p); + c = *q; + *q = 0; + value = sparc_encode_asi (p); + *q = c; + if (value == NULL) + return 0; + *value_p = value; + *input_pointer_p = q; + return 1; +} + /* Parse an argument that can be expressed as a keyword. (eg: #StoreStore or %ccfr). The result is a boolean indicating success. @@ -3261,10 +3303,7 @@ parse_keyword_arg (int (*lookup_fn) (const char *), char c, *p, *q; p = *input_pointerP; - for (q = p + (*p == '#' || *p == '%'); - ISALNUM (*q) || *q == '_'; - ++q) - continue; + q = skip_over_keyword(p); c = *q; *q = 0; value = (*lookup_fn) (p); diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h index c79f20dc5e3..6e8d6d7bc06 100644 --- a/include/opcode/sparc.h +++ b/include/opcode/sparc.h @@ -117,6 +117,14 @@ typedef struct sparc_opcode short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; +/* Struct for ASIs - to handle ASIs introduced in a specific architecture */ +typedef struct +{ + int value; + const char *name; + short architecture; +} sparc_asi; + /* FIXME: Add F_ANACHRONISTIC flag for v9. */ #define F_DELAYED 0x00000001 /* Delayed branch. */ #define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */ @@ -296,7 +304,7 @@ typedef struct sparc_opcode extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; -extern int sparc_encode_asi (const char *); +extern const sparc_asi *sparc_encode_asi (const char *); extern const char *sparc_decode_asi (int); extern int sparc_encode_membar (const char *); extern const char *sparc_decode_membar (int); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ca2cf0e938e..61d35a13ee2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-02-23 Sheldon Lobo + + Add support for associating SPARC ASIs with an architecture level. + * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. + * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ + decoding of SPARC ASIs. + 2017-02-23 Jan Beulich * i386-dis.c (get_valid_dis386): Don't special case VEX opcode diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index a42013933d8..2473de5dc9f 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -2262,6 +2262,195 @@ IMPDEP ("impdep2", 0x37), const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); +/* Handle ASI's. */ + +static sparc_asi asi_table[] = +{ + /* These are in the v9 architecture manual. */ + /* The shorter versions appear first, they're here because Sun's as has them. + Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the + UltraSPARC architecture manual). */ + { 0x04, "#ASI_N", v9 }, + { 0x0c, "#ASI_N_L", v9 }, + { 0x10, "#ASI_AIUP", v9 }, + { 0x11, "#ASI_AIUS", v9 }, + { 0x18, "#ASI_AIUP_L", v9 }, + { 0x19, "#ASI_AIUS_L", v9 }, + { 0x80, "#ASI_P", v9 }, + { 0x81, "#ASI_S", v9 }, + { 0x82, "#ASI_PNF", v9 }, + { 0x83, "#ASI_SNF", v9 }, + { 0x88, "#ASI_P_L", v9 }, + { 0x89, "#ASI_S_L", v9 }, + { 0x8a, "#ASI_PNF_L", v9 }, + { 0x8b, "#ASI_SNF_L", v9 }, + { 0x04, "#ASI_NUCLEUS", v9 }, + { 0x0c, "#ASI_NUCLEUS_LITTLE", v9 }, + { 0x10, "#ASI_AS_IF_USER_PRIMARY", v9 }, + { 0x11, "#ASI_AS_IF_USER_SECONDARY", v9 }, + { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE", v9 }, + { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE", v9 }, + { 0x80, "#ASI_PRIMARY", v9 }, + { 0x81, "#ASI_SECONDARY", v9 }, + { 0x82, "#ASI_PRIMARY_NOFAULT", v9 }, + { 0x83, "#ASI_SECONDARY_NOFAULT", v9 }, + { 0x88, "#ASI_PRIMARY_LITTLE", v9 }, + { 0x89, "#ASI_SECONDARY_LITTLE", v9 }, + { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE", v9 }, + { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE", v9 }, + /* These are UltraSPARC and Niagara extensions. */ + { 0x14, "#ASI_PHYS_USE_EC", v9b }, + { 0x15, "#ASI_PHYS_BYPASS_EC_E", v9b }, + { 0x16, "#ASI_BLK_AIUP_4V", v9c }, + { 0x17, "#ASI_BLK_AIUS_4V", v9c }, + { 0x1c, "#ASI_PHYS_USE_EC_L", v9b }, + { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L", v9b }, + { 0x1e, "#ASI_BLK_AIUP_L_4V", v9c }, + { 0x1f, "#ASI_BLK_AIUS_L_4V", v9c }, + { 0x20, "#ASI_SCRATCHPAD", v9c }, + { 0x21, "#ASI_MMU", v9c }, + { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS", v9c }, + { 0x24, "#ASI_NUCLEUS_QUAD_LDD", v9b }, + { 0x25, "#ASI_QUEUE", v9c }, + { 0x26, "#ASI_QUAD_LDD_PHYS_4V", v9c }, + { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L", v9b }, + { 0x30, "#ASI_PCACHE_DATA_STATUS", v9b }, + { 0x31, "#ASI_PCACHE_DATA", v9b }, + { 0x32, "#ASI_PCACHE_TAG", v9b }, + { 0x33, "#ASI_PCACHE_SNOOP_TAG", v9b }, + { 0x34, "#ASI_QUAD_LDD_PHYS", v9b }, + { 0x38, "#ASI_WCACHE_VALID_BITS", v9b }, + { 0x39, "#ASI_WCACHE_DATA", v9b }, + { 0x3a, "#ASI_WCACHE_TAG", v9b }, + { 0x3b, "#ASI_WCACHE_SNOOP_TAG", v9b }, + { 0x3c, "#ASI_QUAD_LDD_PHYS_L", v9b }, + { 0x40, "#ASI_SRAM_FAST_INIT", v9b }, + { 0x41, "#ASI_CORE_AVAILABLE", v9b }, + { 0x41, "#ASI_CORE_ENABLE_STAT", v9b }, + { 0x41, "#ASI_CORE_ENABLE", v9b }, + { 0x41, "#ASI_XIR_STEERING", v9b }, + { 0x41, "#ASI_CORE_RUNNING_RW", v9b }, + { 0x41, "#ASI_CORE_RUNNING_W1S", v9b }, + { 0x41, "#ASI_CORE_RUNNING_W1C", v9b }, + { 0x41, "#ASI_CORE_RUNNING_STAT", v9b }, + { 0x41, "#ASI_CMT_ERROR_STEERING", v9b }, + { 0x45, "#ASI_LSU_CONTROL_REG", v9b }, + { 0x45, "#ASI_DCU_CONTROL_REG", v9b }, + { 0x46, "#ASI_DCACHE_DATA", v9b }, + { 0x47, "#ASI_DCACHE_TAG", v9b }, + { 0x48, "#ASI_INTR_DISPATCH_STAT", v9b }, + { 0x49, "#ASI_INTR_RECEIVE", v9b }, + { 0x4b, "#ASI_ESTATE_ERROR_EN", v9b }, + { 0x4c, "#ASI_AFSR", v9b }, + { 0x4d, "#ASI_AFAR", v9b }, + { 0x4e, "#ASI_EC_TAG_DATA", v9b }, + { 0x50, "#ASI_IMMU", v9b }, + { 0x51, "#ASI_IMMU_TSB_8KB_PTR", v9b }, + { 0x52, "#ASI_IMMU_TSB_64KB_PTR", v9b }, + { 0x54, "#ASI_ITLB_DATA_IN", v9b }, + { 0x55, "#ASI_ITLB_DATA_ACCESS", v9b }, + { 0x56, "#ASI_ITLB_TAG_READ", v9b }, + { 0x57, "#ASI_IMMU_DEMAP", v9b }, + { 0x58, "#ASI_DMMU", v9b }, + { 0x59, "#ASI_DMMU_TSB_8KB_PTR", v9b }, + { 0x5a, "#ASI_DMMU_TSB_64KB_PTR", v9b }, + { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR", v9b }, + { 0x5c, "#ASI_DTLB_DATA_IN", v9b }, + { 0x5d, "#ASI_DTLB_DATA_ACCESS", v9b }, + { 0x5e, "#ASI_DTLB_TAG_READ", v9b }, + { 0x5f, "#ASI_DMMU_DEMAP", v9b }, + { 0x60, "#ASI_IIU_INST_TRAP", v9b }, + { 0x63, "#ASI_INTR_ID", v9b }, + { 0x63, "#ASI_CORE_ID", v9b }, + { 0x63, "#ASI_CESR_ID", v9b }, + { 0x66, "#ASI_IC_INSTR", v9b }, + { 0x67, "#ASI_IC_TAG", v9b }, + { 0x68, "#ASI_IC_STAG", v9b }, + { 0x6f, "#ASI_BRPRED_ARRAY", v9b }, + { 0x70, "#ASI_BLK_AIUP", v9b }, + { 0x71, "#ASI_BLK_AIUS", v9b }, + { 0x72, "#ASI_MCU_CTRL_REG", v9b }, + { 0x74, "#ASI_EC_DATA", v9b }, + { 0x75, "#ASI_EC_CTRL", v9b }, + { 0x76, "#ASI_EC_W", v9b }, + { 0x77, "#ASI_INTR_W", v9b }, + { 0x77, "#ASI_INTR_DATAN_W", v9b }, + { 0x77, "#ASI_INTR_DISPATCH_W", v9b }, + { 0x78, "#ASI_BLK_AIUPL", v9b }, + { 0x79, "#ASI_BLK_AIUSL", v9b }, + { 0x7e, "#ASI_EC_R", v9b }, + { 0x7f, "#ASI_INTR_R", v9b }, + { 0x7f, "#ASI_INTR_DATAN_R", v9b }, + { 0xc0, "#ASI_PST8_P", v9b }, + { 0xc1, "#ASI_PST8_S", v9b }, + { 0xc2, "#ASI_PST16_P", v9b }, + { 0xc3, "#ASI_PST16_S", v9b }, + { 0xc4, "#ASI_PST32_P", v9b }, + { 0xc5, "#ASI_PST32_S", v9b }, + { 0xc8, "#ASI_PST8_PL", v9b }, + { 0xc9, "#ASI_PST8_SL", v9b }, + { 0xca, "#ASI_PST16_PL", v9b }, + { 0xcb, "#ASI_PST16_SL", v9b }, + { 0xcc, "#ASI_PST32_PL", v9b }, + { 0xcd, "#ASI_PST32_SL", v9b }, + { 0xd0, "#ASI_FL8_P", v9b }, + { 0xd1, "#ASI_FL8_S", v9b }, + { 0xd2, "#ASI_FL16_P", v9b }, + { 0xd3, "#ASI_FL16_S", v9b }, + { 0xd8, "#ASI_FL8_PL", v9b }, + { 0xd9, "#ASI_FL8_SL", v9b }, + { 0xda, "#ASI_FL16_PL", v9b }, + { 0xdb, "#ASI_FL16_SL", v9b }, + { 0xe0, "#ASI_BLK_COMMIT_P", v9b }, + { 0xe1, "#ASI_BLK_COMMIT_S", v9b }, + { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P", v9b }, + { 0xf0, "#ASI_BLK_P", v9b }, + { 0xf1, "#ASI_BLK_S", v9b }, + { 0xf8, "#ASI_BLK_PL", v9b }, + { 0xf9, "#ASI_BLK_SL", v9b }, + { 0x22, "#ASI_TWINX_AIUP", v9c }, + { 0x23, "#ASI_TWINX_AIUS", v9c }, + { 0x26, "#ASI_TWINX_REAL", v9c }, + { 0x27, "#ASI_TWINX_N", v9c }, + { 0x2A, "#ASI_TWINX_AIUP_L", v9c }, + { 0x2B, "#ASI_TWINX_AIUS_L", v9c }, + { 0x2E, "#ASI_TWINX_REAL_L", v9c }, + { 0x2F, "#ASI_TWINX_NL", v9c }, + { 0xE2, "#ASI_TWINX_P", v9c }, + { 0xE3, "#ASI_TWINX_S", v9c }, + { 0xEA, "#ASI_TWINX_PL", v9c }, + { 0xEB, "#ASI_TWINX_SL", v9c }, + { 0, 0, 0 } +}; + +/* Return the a pointer to the matching sparc_asi struct, NULL if not found. */ + +const sparc_asi * +sparc_encode_asi (const char *name) +{ + const sparc_asi *p; + + for (p = asi_table; p->name; ++p) + if (strcmp (name, p->name) == 0) + return p; + + return NULL; +} + +/* Return the name for ASI value VALUE or NULL if not found. */ + +const char * +sparc_decode_asi (int value) +{ + const sparc_asi *p; + + for (p = asi_table; p->name; ++p) + if (value == p->value) + return p->name; + + return NULL; +} + /* Utilities for argument parsing. */ typedef struct @@ -2297,202 +2486,7 @@ lookup_value (const arg *table, int value) return NULL; } - -/* Handle ASI's. */ - -static arg asi_table[] = -{ - /* These are in the v9 architecture manual. */ - /* The shorter versions appear first, they're here because Sun's as has them. - Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the - UltraSPARC architecture manual). */ - { 0x04, "#ASI_N" }, - { 0x0c, "#ASI_N_L" }, - { 0x10, "#ASI_AIUP" }, - { 0x11, "#ASI_AIUS" }, - { 0x18, "#ASI_AIUP_L" }, - { 0x19, "#ASI_AIUS_L" }, - { 0x80, "#ASI_P" }, - { 0x81, "#ASI_S" }, - { 0x82, "#ASI_PNF" }, - { 0x83, "#ASI_SNF" }, - { 0x88, "#ASI_P_L" }, - { 0x89, "#ASI_S_L" }, - { 0x8a, "#ASI_PNF_L" }, - { 0x8b, "#ASI_SNF_L" }, - { 0x04, "#ASI_NUCLEUS" }, - { 0x0c, "#ASI_NUCLEUS_LITTLE" }, - { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, - { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, - { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, - { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, - { 0x80, "#ASI_PRIMARY" }, - { 0x81, "#ASI_SECONDARY" }, - { 0x82, "#ASI_PRIMARY_NOFAULT" }, - { 0x83, "#ASI_SECONDARY_NOFAULT" }, - { 0x88, "#ASI_PRIMARY_LITTLE" }, - { 0x89, "#ASI_SECONDARY_LITTLE" }, - { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, - { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, - /* These are UltraSPARC and Niagara extensions. */ - { 0x14, "#ASI_PHYS_USE_EC" }, - { 0x15, "#ASI_PHYS_BYPASS_EC_E" }, - { 0x16, "#ASI_BLK_AIUP_4V" }, - { 0x17, "#ASI_BLK_AIUS_4V" }, - { 0x1c, "#ASI_PHYS_USE_EC_L" }, - { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" }, - { 0x1e, "#ASI_BLK_AIUP_L_4V" }, - { 0x1f, "#ASI_BLK_AIUS_L_4V" }, - { 0x20, "#ASI_SCRATCHPAD" }, - { 0x21, "#ASI_MMU" }, - { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" }, - { 0x24, "#ASI_NUCLEUS_QUAD_LDD" }, - { 0x25, "#ASI_QUEUE" }, - { 0x26, "#ASI_QUAD_LDD_PHYS_4V" }, - { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" }, - { 0x30, "#ASI_PCACHE_DATA_STATUS" }, - { 0x31, "#ASI_PCACHE_DATA" }, - { 0x32, "#ASI_PCACHE_TAG" }, - { 0x33, "#ASI_PCACHE_SNOOP_TAG" }, - { 0x34, "#ASI_QUAD_LDD_PHYS" }, - { 0x38, "#ASI_WCACHE_VALID_BITS" }, - { 0x39, "#ASI_WCACHE_DATA" }, - { 0x3a, "#ASI_WCACHE_TAG" }, - { 0x3b, "#ASI_WCACHE_SNOOP_TAG" }, - { 0x3c, "#ASI_QUAD_LDD_PHYS_L" }, - { 0x40, "#ASI_SRAM_FAST_INIT" }, - { 0x41, "#ASI_CORE_AVAILABLE" }, - { 0x41, "#ASI_CORE_ENABLE_STAT" }, - { 0x41, "#ASI_CORE_ENABLE" }, - { 0x41, "#ASI_XIR_STEERING" }, - { 0x41, "#ASI_CORE_RUNNING_RW" }, - { 0x41, "#ASI_CORE_RUNNING_W1S" }, - { 0x41, "#ASI_CORE_RUNNING_W1C" }, - { 0x41, "#ASI_CORE_RUNNING_STAT" }, - { 0x41, "#ASI_CMT_ERROR_STEERING" }, - { 0x41, "#ASI_DCACHE_INVALIDATE" }, - { 0x41, "#ASI_DCACHE_UTAG" }, - { 0x41, "#ASI_DCACHE_SNOOP_TAG" }, - { 0x42, "#ASI_DCACHE_INVALIDATE" }, - { 0x43, "#ASI_DCACHE_UTAG" }, - { 0x44, "#ASI_DCACHE_SNOOP_TAG" }, - { 0x45, "#ASI_LSU_CONTROL_REG" }, - { 0x45, "#ASI_DCU_CONTROL_REG" }, - { 0x46, "#ASI_DCACHE_DATA" }, - { 0x47, "#ASI_DCACHE_TAG" }, - { 0x48, "#ASI_INTR_DISPATCH_STAT" }, - { 0x49, "#ASI_INTR_RECEIVE" }, - { 0x4a, "#ASI_UPA_CONFIG" }, - { 0x4a, "#ASI_JBUS_CONFIG" }, - { 0x4a, "#ASI_SAFARI_CONFIG" }, - { 0x4a, "#ASI_SAFARI_ADDRESS" }, - { 0x4b, "#ASI_ESTATE_ERROR_EN" }, - { 0x4c, "#ASI_AFSR" }, - { 0x4d, "#ASI_AFAR" }, - { 0x4e, "#ASI_EC_TAG_DATA" }, - { 0x50, "#ASI_IMMU" }, - { 0x51, "#ASI_IMMU_TSB_8KB_PTR" }, - { 0x52, "#ASI_IMMU_TSB_16KB_PTR" }, - { 0x54, "#ASI_ITLB_DATA_IN" }, - { 0x55, "#ASI_ITLB_DATA_ACCESS" }, - { 0x56, "#ASI_ITLB_TAG_READ" }, - { 0x57, "#ASI_IMMU_DEMAP" }, - { 0x58, "#ASI_DMMU" }, - { 0x59, "#ASI_DMMU_TSB_8KB_PTR" }, - { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" }, - { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" }, - { 0x5c, "#ASI_DTLB_DATA_IN" }, - { 0x5d, "#ASI_DTLB_DATA_ACCESS" }, - { 0x5e, "#ASI_DTLB_TAG_READ" }, - { 0x5f, "#ASI_DMMU_DEMAP" }, - { 0x60, "#ASI_IIU_INST_TRAP" }, - { 0x63, "#ASI_INTR_ID" }, - { 0x63, "#ASI_CORE_ID" }, - { 0x63, "#ASI_CESR_ID" }, - { 0x66, "#ASI_IC_INSTR" }, - { 0x67, "#ASI_IC_TAG" }, - { 0x68, "#ASI_IC_STAG" }, - { 0x6e, "#ASI_IC_PRE_DECODE" }, - { 0x6f, "#ASI_IC_NEXT_FIELD" }, - { 0x6f, "#ASI_BRPRED_ARRAY" }, - { 0x70, "#ASI_BLK_AIUP" }, - { 0x71, "#ASI_BLK_AIUS" }, - { 0x72, "#ASI_MCU_CTRL_REG" }, - { 0x74, "#ASI_EC_DATA" }, - { 0x75, "#ASI_EC_CTRL" }, - { 0x76, "#ASI_EC_W" }, - { 0x77, "#ASI_UDB_ERROR_W" }, - { 0x77, "#ASI_UDB_CONTROL_W" }, - { 0x77, "#ASI_INTR_W" }, - { 0x77, "#ASI_INTR_DATAN_W" }, - { 0x77, "#ASI_INTR_DISPATCH_W" }, - { 0x78, "#ASI_BLK_AIUPL" }, - { 0x79, "#ASI_BLK_AIUSL" }, - { 0x7e, "#ASI_EC_R" }, - { 0x7f, "#ASI_UDBH_ERROR_R" }, - { 0x7f, "#ASI_UDBL_ERROR_R" }, - { 0x7f, "#ASI_UDBH_CONTROL_R" }, - { 0x7f, "#ASI_UDBL_CONTROL_R" }, - { 0x7f, "#ASI_INTR_R" }, - { 0x7f, "#ASI_INTR_DATAN_R" }, - { 0xc0, "#ASI_PST8_P" }, - { 0xc1, "#ASI_PST8_S" }, - { 0xc2, "#ASI_PST16_P" }, - { 0xc3, "#ASI_PST16_S" }, - { 0xc4, "#ASI_PST32_P" }, - { 0xc5, "#ASI_PST32_S" }, - { 0xc8, "#ASI_PST8_PL" }, - { 0xc9, "#ASI_PST8_SL" }, - { 0xca, "#ASI_PST16_PL" }, - { 0xcb, "#ASI_PST16_SL" }, - { 0xcc, "#ASI_PST32_PL" }, - { 0xcd, "#ASI_PST32_SL" }, - { 0xd0, "#ASI_FL8_P" }, - { 0xd1, "#ASI_FL8_S" }, - { 0xd2, "#ASI_FL16_P" }, - { 0xd3, "#ASI_FL16_S" }, - { 0xd8, "#ASI_FL8_PL" }, - { 0xd9, "#ASI_FL8_SL" }, - { 0xda, "#ASI_FL16_PL" }, - { 0xdb, "#ASI_FL16_SL" }, - { 0xe0, "#ASI_BLK_COMMIT_P", }, - { 0xe1, "#ASI_BLK_COMMIT_S", }, - { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" }, - { 0xf0, "#ASI_BLK_P", }, - { 0xf1, "#ASI_BLK_S", }, - { 0xf8, "#ASI_BLK_PL", }, - { 0xf9, "#ASI_BLK_SL", }, - { 0x22, "#ASI_TWINX_AIUP", }, - { 0x23, "#ASI_TWINX_AIUS", }, - { 0x26, "#ASI_TWINX_REAL", }, - { 0x27, "#ASI_TWINX_N", }, - { 0x2A, "#ASI_TWINX_AIUP_L", }, - { 0x2B, "#ASI_TWINX_AIUS_L", }, - { 0x2E, "#ASI_TWINX_REAL_L", }, - { 0x2F, "#ASI_TWINX_NL", }, - { 0xE2, "#ASI_TWINX_P", }, - { 0xE3, "#ASI_TWINX_S", }, - { 0xEA, "#ASI_TWINX_PL", }, - { 0xEB, "#ASI_TWINX_SL", }, - { 0, 0 } -}; -/* Return the value for ASI NAME, or -1 if not found. */ - -int -sparc_encode_asi (const char *name) -{ - return lookup_name (asi_table, name); -} - -/* Return the name for ASI value VALUE or NULL if not found. */ - -const char * -sparc_decode_asi (int value) -{ - return lookup_value (asi_table, value); -} - /* Handle membar masks. */ static arg membar_table[] =