From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Dec 2019 21:56:13 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

1ea1e8e54f33e4a048c1343959e20e8f1c8ad73b
diff --cc techlibs/xilinx/cells_sim.v
index d7dff8975,47ba794bf..5d589bd2f
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -281,9 -313,18 +313,19 @@@ endmodul
  
  `endif
  
+ module ORCY (output O, input CI, I);
+   assign O = CI | I;
+ endmodule
+ 
+ module MULT_AND (output LO, input I0, I1);
+   assign LO = I0 & I1;
+ endmodule
+ 
+ // Flip-flops and latches.
+ 
  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
  
 +(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
  module FDRE (
    (* abc9_arrival=303 *)
    output reg Q,
@@@ -386,16 -435,73 +428,61 @@@ module FDCE_1 
    (* abc9_arrival=303 *)
    output reg Q,
    (* clkbuf_sink *)
 -  (* invertible_pin = "IS_C_INVERTED" *)
    input C,
 -  input CE,
 -  (* invertible_pin = "IS_D_INVERTED" *)
 -  input D,
 -  (* invertible_pin = "IS_PRE_INVERTED" *)
 -  input PRE
 +  input CE, D, CLR
  );
 -  parameter [0:0] INIT = 1'b1;
 -  parameter [0:0] IS_C_INVERTED = 1'b0;
 -  parameter [0:0] IS_D_INVERTED = 1'b0;
 -  parameter [0:0] IS_PRE_INVERTED = 1'b0;
 +  parameter [0:0] INIT = 1'b0;
    initial Q <= INIT;
 -  generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 -    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 -  endcase endgenerate
 +  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
  endmodule
  
+ module FDCPE (
+   output wire Q,
+   (* clkbuf_sink *)
+   (* invertible_pin = "IS_C_INVERTED" *)
+   input C,
+   input CE,
+   (* invertible_pin = "IS_CLR_INVERTED" *)
+   input CLR,
+   input D,
+   (* invertible_pin = "IS_PRE_INVERTED" *)
+   input PRE
+ );
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_C_INVERTED = 1'b0;
+   parameter [0:0] IS_CLR_INVERTED = 1'b0;
+   parameter [0:0] IS_PRE_INVERTED = 1'b0;
+   wire c = C ^ IS_C_INVERTED;
+   wire clr = CLR ^ IS_CLR_INVERTED;
+   wire pre = PRE ^ IS_PRE_INVERTED;
+   // Hacky model to avoid simulation-synthesis mismatches.
+   reg qc, qp, qs;
+   initial qc = INIT;
+   initial qp = INIT;
+   initial qs = 0;
+   always @(posedge c, posedge clr) begin
+     if (clr)
+       qc <= 0;
+     else if (CE)
+       qc <= D;
+   end
+   always @(posedge c, posedge pre) begin
+     if (pre)
+       qp <= 1;
+     else if (CE)
+       qp <= D;
+   end
+   always @* begin
+     if (clr)
+       qs <= 0;
+     else if (pre)
+       qs <= 1;
+   end
+   assign Q = qs ? qp : qc;
+ endmodule
+ 
 -module FDRE_1 (
 +(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
 +module FDPE (
    (* abc9_arrival=303 *)
    output reg Q,
    (* clkbuf_sink *)