From: lkcl <lkcl@web>
Date: Sat, 4 Jun 2022 20:23:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1968
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ea3451097884154394519ed23d74e8baf79d6bf;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e96ac72a2..67455212a 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -92,6 +92,11 @@ is under severe design pressure as it is insufficient to hold
 the full extent of the instruction additions required to create
 a Hybrid 3D CPU-VPU-GPU.
 
+**Whilst SVP64 is only 4 instructions
+the heavy focus on VSX for the past 12 years has left the SFFS Level
+anaemic and out-of-date compared to ARM and x86. Approximately
+100 additional Scalar Instructions are up for proposal**
+
 # Sub-pages
 
 Pages being developed and examples