From: Sandipan Das Date: Sat, 6 Feb 2021 11:51:57 +0000 (+0530) Subject: arch-power: Refactor rotate instructions X-Git-Tag: develop-gem5-snapshot~22 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1eb197fc82e3f2a34e53e519631a777410d589e9;p=gem5.git arch-power: Refactor rotate instructions This renames the mask span fields and the rotate helper of the base class. Change-Id: I120006a0c052fcc34eb154a68d4b7f70a464df65 Signed-off-by: Sandipan Das --- diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index fc429117c..d921b5d1b 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -729,7 +729,7 @@ IntRotateOp::generateDisassembly( } // Print the shift, mask begin and mask end - ss << ", " << sh << ", " << mb << ", " << me; + ss << ", " << sh << ", " << maskBeg << ", " << maskEnd; return ss.str(); } diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index aab6910bc..d96936291 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -643,31 +643,33 @@ class IntConcatShiftOp : public IntOp /** - * Class for integer rotate operations. + * Class for integer rotate operations with a shift amount obtained + * from a register or an immediate and the first and last bits of a + * mask obtained from immediates. */ class IntRotateOp : public IntShiftOp { protected: - uint32_t mb; - uint32_t me; uint32_t fullMask; + uint32_t maskBeg; + uint32_t maskEnd; /// Constructor IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass) : IntShiftOp(mnem, _machInst, __opClass), - mb(machInst.mb), - me(machInst.me) + maskBeg(machInst.mb), + maskEnd(machInst.me) { - if (me >= mb) { - fullMask = mask(31 - mb, 31 - me); + if (maskEnd >= maskBeg) { + fullMask = mask(31 - maskBeg, 31 - maskEnd); } else { - fullMask = ~mask(31 - (me + 1), 31 - (mb - 1)); + fullMask = ~mask(31 - (maskEnd + 1), 31 - (maskBeg - 1)); } } - uint32_t - rotateValue(uint32_t rs, uint32_t shift) const + inline uint32_t + rotate(uint32_t rs, uint32_t sh) const { uint32_t n = shift & 31; return (rs << n) | (rs >> (32 - n)); diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index e99769961..ef66ac95d 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -266,9 +266,9 @@ decode PO default Unknown::unknown() { } format IntRotateOp { - 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }}); - 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }}); - 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | + 21: rlwinm({{ Ra = rotate(Rs, sh) & fullMask; }}); + 23: rlwnm({{ Ra = rotate(Rs, Rb) & fullMask; }}); + 20: rlwimi({{ Ra = (rotate(Rs, sh) & fullMask) | (Ra & ~fullMask); }}); } diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa index 571a1b6ed..bc52340ec 100644 --- a/src/arch/power/isa/formats/integer.isa +++ b/src/arch/power/isa/formats/integer.isa @@ -526,15 +526,17 @@ def format IntConcatShiftOp(code, computeCA = 0, inst_flags = []) {{ }}; -// A special format for rotate instructions which use certain fields -// from the instruction's binary encoding. We need two versions for each -// instruction to deal with the Rc bit. +// Integer instructions with or without immediate that perform rotate +// operations. All instructions write to Ra and use Rs as a source +// register. If immediate is not used, Rb is also used as a source +// register. We need two versions for each instruction to deal with +// the Rc bit. def format IntRotateOp(code, inst_flags = []) {{ # The result is always in Ra dict = {'result':'Ra'} - # Setup the code for when Rc is set + # Code when Rc is set code_rc1 = readXERCode + code + computeCR0Code % dict # Generate the first class