From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 6 Feb 2012 17:07:02 +0000 (+0100)
Subject: fhdl: do not attempt slicing non-array signals to keep Verilog happy
X-Git-Tag: 24jan2021_ls180~2099^2~1038
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1eb348c573dfb68c67ed09445e5fdb5f524ac8b6;p=litex.git

fhdl: do not attempt slicing non-array signals to keep Verilog happy
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index f169b508..4af82bd5 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -34,6 +34,12 @@ def _printexpr(ns, node):
 			raise TypeError
 		return "(" + r + ")"
 	elif isinstance(node, _Slice):
+		# Verilog does not like us slicing non-array signals...
+		if isinstance(node.value, Signal) \
+		  and node.value.bv.width == 1 \
+		  and node.start == 0 and node.stop == 1:
+			  return _printexpr(ns, node.value)
+
 		if node.start + 1 == node.stop:
 			sr = "[" + str(node.start) + "]"
 		else: