From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 02:31:27 +0000 (+0000)
Subject: add example illustrative tables
X-Git-Tag: convert-csv-opcode-to-binary~4882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ebbc267e8c0092607d39c908ce8c88364d18cea;p=libreriscv.git

add example illustrative tables
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index cb7e21329..8cc5f9dd5 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1551,11 +1551,13 @@ Note:
 
 LH - 16-bit load, to elwidth 32-bit
 
+[[!table  data="""
 | addr | byte 0 | byte 1 | byte 2 | byte 3 | byte 4 | byte 5 | byte 6 | byte 7 |
+| ---- | ------ | ------ | ------ | ------ | ------ | ------ | ------ | ------ |
 | @x5  | elem 0         || elem 1         || elem 2         || elem 3         ||
 | @x6  | elem 4         || elem 5         || elem 6         || elem 7         ||
 | .... | ...... | ...... | ...... | ...... | ...... | ...... | ...... | ...... |
-
+"""]]
 
 ## Why SV bitwidth specification is restricted to 4 entries