From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 21:43:45 +0000 (-0700)
Subject: Cope with inout ports
X-Git-Tag: working-ls180~1237^2~206
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ec5f18346dd3f50e2340f4b79239a045ce7dd72;p=yosys.git

Cope with inout ports
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 070d6d403..14fa4fb7f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -197,9 +197,12 @@ struct XAigerWriter
 						continue;
 				}
 
-				if (cell->input(conn.first))
+				if (cell->input(conn.first)) {
+					// Ignore inout for the sake of topographical ordering
+					if (cell->output(conn.first)) continue;
 					for (auto bit : sigmap(conn.second))
 						bit_users[bit].insert(cell->name);
+				}
 
 				if (cell->output(conn.first))
 					for (auto bit : sigmap(conn.second))
@@ -287,7 +290,18 @@ struct XAigerWriter
 					for (auto user_cell : it.second)
 						toposort.edge(driver_cell, user_cell);
 
+#ifndef NDEBUG
+			toposort.analyze_loops = true;
+#endif
 			toposort.sort();
+#ifndef NDEBUG
+			for (auto &it : toposort.loops) {
+				log("  loop");
+				for (auto cell : it)
+					log(" %s", log_id(cell));
+				log("\n");
+			}
+#endif
 			log_assert(!toposort.found_loops);
 
 			for (auto cell_name : toposort.sorted) {