From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 16:02:42 +0000 (-0700)
Subject: Tidy up
X-Git-Tag: working-ls180~1208^2~366
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ec949d5edfb6b13b8bf412763ae272a47fec894;p=yosys.git

Tidy up
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 4f5c7ff18..ff33cf8ff 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -53,7 +53,7 @@ module \$shiftx (A, B, Y);
       for (i = 0; i < B_WIDTH; i++)
 	if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
-        else if (i == num_mux8 && A_WIDTH > i*a_width0)
+        else if (i == num_mux8 && a_widthN > 0)
 	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         else
 	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};