From: lkcl <lkcl@web>
Date: Tue, 5 Jan 2021 01:28:37 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~618
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ecd4de36658f6ec98fd7e4ca3f6bdb6399abe35;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 39e1c3e57..85f7e9038 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -515,7 +515,7 @@ definition, and its members are defined as being in LE order. From there,
 implementations may choose whatever internal HDL wire order they like
 as long as the results produced conform to the elwidth pseudocode.
 
-*Note: it turns out that both x86 SIMD and NEON SIMD follow this convention, namely that both are implicitly LE, even though their ISA Manuals may not explicitly spell this out
+*Note: it turns out that both x86 SIMD and NEON SIMD follow this convention, namely that both are implicitly LE, even though their ISA Manuals may not explicitly spell this out*
 
 * <https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Endian-support/Endianness-in-Advanced-SIMD?lang=en>
 * <https://stackoverflow.com/questions/24045102/how-does-endianness-work-with-simd-registers>