From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 15:38:10 +0000 (+0100)
Subject: add rlwinm. test instruction (sets CR0)
X-Git-Tag: div_pipeline~687
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ed95c219f90444fbf862a439d5a51d8a565d7aa;p=soc.git

add rlwinm. test instruction (sets CR0)
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 8b942fcf..2a4ad4b7 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -129,7 +129,8 @@ class ShiftRotTestCase(FHDLTestCase):
             mb = random.randint(0,31)
             me = random.randint(0,31)
             sh = random.randint(0,31)
-            lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"]
+            lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
+                   f"rlwinm. 3, 1, {mb}, {me}, {sh}"]
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)