From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 11:12:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1760
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ede041ddb88c35b356808527cf0764c8f2cd24e;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 5720c3d9a..0ec81e92b 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -2,7 +2,8 @@
 
 # SV Vector Operations.
 
-TODO merge old standards page [[simple_v_extension/vector_ops/]]
+* TODO merge old standards page [[simple_v_extension/vector_ops/]]
+* bugreport <https://bugs.libre-soc.org/show_bug.cgi?id=142>
 
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)