From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Apr 2021 15:25:05 +0000 (+0100)
Subject: comments on dcache-to-mmu link
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ee32dee81f0d890e7b8607db91b5694c196a636;p=soc.git

comments on dcache-to-mmu link
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index a21b73da..00b537d6 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -262,8 +262,8 @@ class FSMMMUStage(ControlBase):
         # link mmu and dcache together
         m.submodules.mmu = mmu = self.mmu
         ldst = self.ldst # managed externally: do not add here
-        m.d.comb += dcache.m_in.eq(mmu.d_out)
-        m.d.comb += mmu.d_in.eq(dcache.m_out)
+        m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
+        m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 
         l_in, l_out = mmu.l_in, mmu.l_out
         d_in, d_out = dcache.d_in, dcache.d_out