From: Sean Cross Date: Thu, 28 Jun 2018 01:18:42 +0000 (+0800) Subject: soc: integration: use the new cpu_debugging flag for vexriscv X-Git-Tag: 24jan2021_ls180~1685^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ef127e06db03fa30ed9ab6612d7e2e93b893fb5;p=litex.git soc: integration: use the new cpu_debugging flag for vexriscv Allow a new cpu_debugging flag to be passed to the constructor to enable in-circuit live debugging of the softcore under gdb. Signed-off-by: Sean Cross --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 62cb9556..50feab0b 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -61,7 +61,7 @@ class SoCCore(Module): "csr": 0x60000000, # (default shadow @0xe0000000) } def __init__(self, platform, clk_freq, - cpu_type="lm32", cpu_reset_address=0x00000000, cpu_variant=None, + cpu_type="lm32", cpu_reset_address=0x00000000, cpu_variant=None, cpu_debugging=False, integrated_rom_size=0, integrated_rom_init=[], integrated_sram_size=4096, integrated_main_ram_size=0, integrated_main_ram_init=[], @@ -81,6 +81,7 @@ class SoCCore(Module): if integrated_rom_size: cpu_reset_address = self.mem_map["rom"] self.cpu_reset_address = cpu_reset_address + self.cpu_debugging = cpu_debugging self.config["CPU_RESET_ADDR"] = self.cpu_reset_address self.integrated_rom_size = integrated_rom_size @@ -111,7 +112,7 @@ class SoCCore(Module): elif cpu_type == "picorv32": self.add_cpu_or_bridge(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) elif cpu_type == "vexriscv": - self.add_cpu_or_bridge(vexriscv.VexRiscv(platform, self.cpu_reset_address)) + self.add_cpu_or_bridge(vexriscv.VexRiscv(platform, self.cpu_reset_address, cpu_debugging=self.cpu_debugging)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) self.add_wb_master(self.cpu_or_bridge.ibus)