From: Bobby R. Bruce <bbruce@ucdavis.edu>
Date: Mon, 31 Aug 2020 21:43:45 +0000 (-0700)
Subject: arch-arm,arch-x86: Added missing overrides
X-Git-Tag: v20.1.0.0~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f01fa91f7fa8ed7f55243f273fce27859c40210;p=gem5.git

arch-arm,arch-x86: Added missing overrides

These overrides were missing, causing compilation errors when
compiling with clang 9. Noted here:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35657.html

Change-Id: I6d09a0e57af3131b9172d01468d2cdcf4b444c5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33817
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index 98c06fca5..bbb1cc8c6 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -58,7 +58,7 @@ class BranchImm : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with an immediate
@@ -88,7 +88,7 @@ class BranchReg : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with a register
@@ -119,7 +119,7 @@ class BranchRegReg : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with an immediate and a register
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index c7bd0ee11..ad736c204 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -54,7 +54,7 @@ class MightBeMicro : public PredOp
     {}
 
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop]) {
             pcState.uEnd();
@@ -372,7 +372,8 @@ class MemoryOffset : public Base
     {}
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_Offset);
@@ -422,7 +423,8 @@ class MemoryPreIndex : public Base
     {}
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_PreIndex);
@@ -472,7 +474,8 @@ class MemoryPostIndex : public Base
     {}
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_PostIndex);
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index eb9ca5450..412efb0ad 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -72,7 +72,7 @@ class MightBeMicro64 : public ArmStaticInst
     {}
 
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop]) {
             pcState.uEnd();
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index 8ba85c21c..aa8d5d096 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -387,7 +387,7 @@ class PredMicroop : public PredOp
     }
 
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop])
             pcState.uEnd();
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index 7b385f109..30a98264e 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -128,7 +128,8 @@ class IllegalExecInst : public ArmStaticInst
   public:
     IllegalExecInst(ExtMachInst _machInst);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 };
 
 class DebugStep : public ArmStaticInst
@@ -136,7 +137,8 @@ class DebugStep : public ArmStaticInst
   public:
     DebugStep(ExtMachInst _machInst);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 };
 
 #endif
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 36f2ad11f..c0fa29c9a 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -66,7 +66,7 @@ class SveIndexIIOp : public ArmStaticInst {
         dest(_dest), imm1(_imm1), imm2(_imm2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexIROp : public ArmStaticInst {
@@ -82,7 +82,7 @@ class SveIndexIROp : public ArmStaticInst {
           dest(_dest), imm1(_imm1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexRIOp : public ArmStaticInst {
@@ -98,7 +98,7 @@ class SveIndexRIOp : public ArmStaticInst {
         dest(_dest), op1(_op1), imm2(_imm2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexRROp : public ArmStaticInst {
@@ -114,7 +114,7 @@ class SveIndexRROp : public ArmStaticInst {
         dest(_dest), op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 // Predicate count SVE instruction.
@@ -133,7 +133,7 @@ class SvePredCountOp : public ArmStaticInst {
         srcIs32b(_srcIs32b), destIsVec(_destIsVec)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 // Predicate count SVE instruction (predicated).
@@ -150,7 +150,7 @@ class SvePredCountPredOp : public ArmStaticInst {
         dest(_dest), op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// While predicate generation SVE instruction.
@@ -166,7 +166,7 @@ class SveWhileOp : public ArmStaticInst {
         dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Compare and terminate loop SVE instruction.
@@ -180,7 +180,7 @@ class SveCompTermOp : public ArmStaticInst {
         op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Unary, constructive, predicated (merging) SVE instruction.
@@ -195,7 +195,7 @@ class SveUnaryPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Unary, constructive, unpredicated SVE instruction.
@@ -210,7 +210,7 @@ class SveUnaryUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Unary with wide immediate, constructive, unpredicated SVE instruction.
@@ -227,7 +227,7 @@ class SveUnaryWideImmUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Unary with wide immediate, constructive, predicated SVE instruction.
@@ -247,7 +247,7 @@ class SveUnaryWideImmPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate, destructive, unpredicated SVE instruction.
@@ -264,7 +264,7 @@ class SveBinImmUnpredConstrOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate, destructive, predicated (merging) SVE instruction.
@@ -280,7 +280,7 @@ class SveBinImmPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with wide immediate, destructive, unpredicated SVE instruction.
@@ -297,7 +297,7 @@ class SveBinWideImmUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, destructive, predicated (merging) SVE instruction.
@@ -313,7 +313,7 @@ class SveBinDestrPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, constructive, predicated SVE instruction.
@@ -331,7 +331,7 @@ class SveBinConstrPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, unpredicated SVE instruction with indexed operand
@@ -346,7 +346,7 @@ class SveBinUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, unpredicated SVE instruction
@@ -363,7 +363,7 @@ class SveBinIdxUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Predicate logical instruction.
@@ -380,7 +380,7 @@ class SvePredLogicalOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Predicate binary permute instruction.
@@ -396,7 +396,7 @@ class SvePredBinPermOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE compare instructions, predicated (zeroing).
@@ -412,7 +412,7 @@ class SveCmpOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE compare-with-immediate instructions, predicated (zeroing).
@@ -429,7 +429,7 @@ class SveCmpImmOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Ternary, destructive, predicated (merging) SVE instruction.
@@ -445,7 +445,7 @@ class SveTerPredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Ternary with immediate, destructive, unpredicated SVE instruction.
@@ -462,7 +462,7 @@ class SveTerImmUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE reductions.
@@ -477,7 +477,7 @@ class SveReducOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE ordered reductions.
@@ -492,7 +492,7 @@ class SveOrdReducOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// PTRUE, PTRUES.
@@ -508,7 +508,7 @@ class SvePtrueOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Integer compare SVE instruction.
@@ -526,7 +526,7 @@ class SveIntCmpOp : public ArmStaticInst {
         dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Integer compare with immediate SVE instruction.
@@ -544,7 +544,7 @@ class SveIntCmpImmOp : public ArmStaticInst {
         dest(_dest), op1(_op1), imm(_imm), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// ADR.
@@ -570,7 +570,7 @@ class SveAdrOp : public ArmStaticInst {
         offsetFormat(_offsetFormat)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Element count SVE instruction.
@@ -591,7 +591,7 @@ class SveElemCountOp : public ArmStaticInst {
         dstIs32b(_dstIs32b)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Partition break SVE instruction.
@@ -609,7 +609,7 @@ class SvePartBrkOp : public ArmStaticInst {
         dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Partition break with propagation SVE instruction.
@@ -627,7 +627,7 @@ class SvePartBrkPropOp : public ArmStaticInst {
         dest(_dest), op1(_op1), op2(_op2), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Scalar element select SVE instruction.
@@ -651,7 +651,7 @@ class SveSelectOp : public ArmStaticInst {
         scalar(_scalar), simdFp(_simdFp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary operation on predicate (predicated)
@@ -668,7 +668,7 @@ class SveUnaryPredPredOp : public ArmStaticInst {
         dest(_dest), op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE table lookup/permute using vector of element indices (TBL)
@@ -684,7 +684,7 @@ class SveTblOp : public ArmStaticInst {
         dest(_dest), op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unpack and widen predicate
@@ -699,7 +699,7 @@ class SveUnpackOp : public ArmStaticInst {
         dest(_dest), op1(_op1)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE predicate test
@@ -714,7 +714,7 @@ class SvePredTestOp : public ArmStaticInst {
         op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit source operand
@@ -728,7 +728,7 @@ class SvePredUnaryWImplicitSrcOp : public ArmStaticInst {
         dest(_dest)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions, predicated, with implicit source operand
@@ -744,7 +744,7 @@ class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst {
         dest(_dest), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit destination operand
@@ -758,7 +758,7 @@ class SvePredUnaryWImplicitDstOp : public ArmStaticInst {
         op1(_op1)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit destination operand
@@ -769,7 +769,7 @@ class SveWImplicitSrcDstOp : public ArmStaticInst {
         ArmStaticInst(mnem, _machInst, __opClass)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE vector - immediate binary operation
@@ -786,7 +786,7 @@ class SveBinImmUnpredDestrOp : public ArmStaticInst {
         dest(_dest), op1(_op1), imm(_imm)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate index, destructive, unpredicated SVE instruction.
@@ -803,7 +803,7 @@ class SveBinImmIdxUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// Unary unpredicated scalar to vector instruction
@@ -820,7 +820,7 @@ class SveUnarySca2VecUnpredOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE dot product instruction (indexed)
@@ -839,7 +839,7 @@ class SveDotProdIdxOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE dot product instruction (vectors)
@@ -857,7 +857,7 @@ class SveDotProdOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE Complex Instructions (vectors)
@@ -875,7 +875,7 @@ class SveComplexOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 /// SVE Complex Instructions (indexed)
@@ -893,7 +893,7 @@ class SveComplexIdxOp : public ArmStaticInst {
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index ed937a230..c38c938d0 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -86,14 +86,15 @@ class SveLdStructSS : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -158,14 +159,15 @@ class SveStStructSS : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -230,14 +232,15 @@ class SveLdStructSI : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -303,14 +306,15 @@ class SveStStructSI : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -402,14 +406,15 @@ class SveIndexedMemVI : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         // TODO: add suffix to transfer and base registers
         std::stringstream ss;
@@ -506,14 +511,15 @@ class SveIndexedMemSV : public PredMacroOp
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
         return NoFault;
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         // TODO: add suffix to transfer and base registers
         std::stringstream ss;
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index 157bc17ef..ebf1428a9 100644
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -67,7 +67,7 @@ class SveMemVecFillSpill : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveMemPredFillSpill : public ArmStaticInst
@@ -93,7 +93,7 @@ class SveMemPredFillSpill : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveContigMemSS : public ArmStaticInst
@@ -120,7 +120,7 @@ class SveContigMemSS : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 class SveContigMemSI : public ArmStaticInst
@@ -147,7 +147,7 @@ class SveContigMemSI : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const;
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };
 
 }  // namespace ArmISA
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index b58f00255..ae3b36d6e 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -849,7 +849,7 @@ class FpOp : public PredOp
             bool flush, uint32_t rMode) const;
 
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop]) {
             pcState.uEnd();
diff --git a/src/arch/arm/isa/templates/sve.isa b/src/arch/arm/isa/templates/sve.isa
index 0bcf27fa9..f460e0ec1 100644
--- a/src/arch/arm/isa/templates/sve.isa
+++ b/src/arch/arm/isa/templates/sve.isa
@@ -64,7 +64,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -85,7 +85,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -106,7 +106,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -127,7 +127,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -148,7 +148,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -191,7 +191,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -212,7 +212,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -233,7 +233,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -255,7 +255,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -276,7 +276,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -298,7 +298,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -320,7 +320,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -342,7 +342,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -364,7 +364,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -386,7 +386,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -408,7 +408,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -429,7 +429,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -450,7 +450,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -475,7 +475,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -496,7 +496,7 @@ class SveIndexII : public SveIndexIIOp
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -517,7 +517,7 @@ class SveIndexIR : public SveIndexIROp
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -538,7 +538,7 @@ class SveIndexRI : public SveIndexRIOp
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -559,7 +559,7 @@ class SveIndexRR : public SveIndexRROp
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -579,7 +579,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -599,7 +599,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 
 }};
@@ -621,7 +621,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -643,7 +643,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -663,7 +663,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -681,7 +681,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -701,7 +701,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -722,7 +722,7 @@ class %(class_name)s : public %(base_class)s
         esize = sizeof(Element);
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -738,7 +738,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -756,7 +756,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -777,7 +777,7 @@ class %(class_name)s : public %(base_class)s
         scalar_width = (sizeof(Element) == 8) ? 64 : 32;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -800,7 +800,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -814,7 +814,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -828,7 +828,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -842,7 +842,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -856,7 +856,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -870,7 +870,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -896,7 +896,7 @@ class %(class_name)s : public %(base_class)s
         esize = sizeof(Element);
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -921,7 +921,7 @@ class %(class_name)s : public %(base_class)s
         esize = sizeof(Element);
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -943,7 +943,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -965,7 +965,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index b5c2dc0ba..e1f725c71 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -50,12 +50,14 @@ def template SveMemFillSpillOpDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -78,12 +80,13 @@ def template SveContigMemSSOpDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) {
+        annotateFault(ArmFault *fault) override {
             %(fa_code)s
         }
     };
@@ -106,12 +109,13 @@ def template SveContigMemSIOpDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault) {
+        annotateFault(ArmFault *fault) override {
             %(fa_code)s
         }
     };
@@ -420,18 +424,20 @@ def template SveIndexedMemVIMicroopDeclare {{
             }
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault)
+        annotateFault(ArmFault *fault) override
         {
             %(fa_code)s
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             // TODO: add suffix to transfer register
             std::stringstream ss;
@@ -499,18 +505,20 @@ def template SveIndexedMemSVMicroopDeclare {{
             }
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault)
+        annotateFault(ArmFault *fault) override
         {
             %(fa_code)s
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             // TODO: add suffix to transfer and base registers
             std::stringstream ss;
@@ -732,10 +740,11 @@ def template SveFirstFaultWritebackMicroopDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -787,10 +796,11 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -851,18 +861,20 @@ def template SveStructMemSIMicroopDeclare {{
             baseIsSP = isSP(_base);
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault)
+        annotateFault(ArmFault *fault) override
         {
             %(fa_code)s
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             printMnemonic(ss, "", false);
@@ -1114,18 +1126,20 @@ def template SveStructMemSSMicroopDeclare {{
             baseIsSP = isSP(_base);
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
         virtual void
-        annotateFault(ArmFault *fault)
+        annotateFault(ArmFault *fault) override
         {
             %(fa_code)s
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             printMnemonic(ss, "", false);
@@ -1187,10 +1201,11 @@ def template SveIntrlvMicroopDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -1224,10 +1239,11 @@ def template SveDeIntrlvMicroopDeclare {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh
index 30a8d4fd1..5b27127e9 100644
--- a/src/arch/x86/insts/macroop.hh
+++ b/src/arch/x86/insts/macroop.hh
@@ -73,7 +73,7 @@ class MacroopBase : public X86StaticInst
     StaticInstPtr * microops;
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         if (microPC >= numMicroops)
             return badMicroop;
@@ -82,7 +82,8 @@ class MacroopBase : public X86StaticInst
     }
 
     std::string
-    generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    generateDisassembly(Addr pc,
+                        const Loader::SymbolTable *symtab) const override
     {
         return mnemonic;
     }
diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh
index d13af317b..f1dc15b22 100644
--- a/src/arch/x86/insts/microfpop.hh
+++ b/src/arch/x86/insts/microfpop.hh
@@ -75,7 +75,7 @@ namespace X86ISA
         bool checkCondition(uint64_t flags) const;*/
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
     };
 }
 
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 6994584c8..1ec31cae6 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -113,7 +113,7 @@ namespace X86ISA
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -147,7 +147,7 @@ namespace X86ISA
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
     };
 }
 
diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh
index 79b1158a2..867ac0ef2 100644
--- a/src/arch/x86/insts/micromediaop.hh
+++ b/src/arch/x86/insts/micromediaop.hh
@@ -104,7 +104,7 @@ namespace X86ISA
         {}
 
         std::string generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const;
+            const Loader::SymbolTable *symtab) const override;
     };
 
     class MediaOpImm : public MediaOpBase
@@ -125,7 +125,7 @@ namespace X86ISA
         {}
 
         std::string generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const;
+            const Loader::SymbolTable *symtab) const override;
     };
 }
 
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index 151de448a..e958fbafb 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -110,7 +110,8 @@ namespace X86ISA
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                           const Loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
 
@@ -122,7 +123,7 @@ namespace X86ISA
         bool checkCondition(uint64_t flags, int condition) const;
 
         void
-        advancePC(PCState &pcState) const
+        advancePC(PCState &pcState) const override
         {
             if (flags[IsLastMicroop])
                 pcState.uEnd();
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index b1d103968..c14d3326a 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -93,7 +93,7 @@ namespace X86ISA
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
     };
 
     class RegOpImm : public RegOpBase
@@ -115,7 +115,7 @@ namespace X86ISA
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
     };
 }
 
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index 2bf93b6b1..bdf82d899 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -87,7 +87,7 @@ namespace X86ISA
             }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
 
         void printMnemonic(std::ostream &os, const char * mnemonic) const;
         void printMnemonic(std::ostream &os, const char * instMnemonic,
@@ -175,7 +175,7 @@ namespace X86ISA
         }
 
         void
-        advancePC(PCState &pcState) const
+        advancePC(PCState &pcState) const override
         {
             pcState.advance();
         }
diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa
index bea8b6a73..cd9ec9e98 100644
--- a/src/arch/x86/isa/formats/basic.isa
+++ b/src/arch/x86/isa/formats/basic.isa
@@ -46,7 +46,7 @@ def template BasicDeclare {{
           public:
             // Constructor.
             %(class_name)s(ExtMachInst machInst);
-            Fault execute(ExecContext *, Trace::InstRecord *) const;
+            Fault execute(ExecContext *, Trace::InstRecord *) const override;
         };
 }};
 
diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa
index f4ed015f7..41e2ac205 100644
--- a/src/arch/x86/isa/formats/cpuid.isa
+++ b/src/arch/x86/isa/formats/cpuid.isa
@@ -48,7 +48,7 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index 0733a2aab..809623de0 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -15,7 +15,7 @@ output header {{
         { }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -50,9 +50,10 @@ def template MwaitDeclare {{
         public:
         // Constructor.
         %(class_name)s(ExtMachInst machInst);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -94,7 +95,7 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa
index 1a708d175..1f52c31eb 100644
--- a/src/arch/x86/isa/formats/nop.isa
+++ b/src/arch/x86/isa/formats/nop.isa
@@ -54,7 +54,7 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa
index f728d7d96..d4402d8bb 100644
--- a/src/arch/x86/isa/formats/syscall.isa
+++ b/src/arch/x86/isa/formats/syscall.isa
@@ -54,7 +54,7 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index b3e21ac3c..066ca595e 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -60,10 +60,11 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const;
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -91,10 +92,11 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const;
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa
index b24928db8..9d1f5bf57 100644
--- a/src/arch/x86/isa/formats/unknown.isa
+++ b/src/arch/x86/isa/formats/unknown.isa
@@ -55,10 +55,10 @@ output header {{
         {
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const;
+                Addr pc, const Loader::SymbolTable *symtab) const override;
 
     };
 }};
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 28753ba42..ccd065a6c 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -42,7 +42,8 @@
 
 // Execute method for macroops.
 def template MacroExecPanic {{
-    Fault execute(ExecContext *, Trace::InstRecord *) const
+    Fault
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Tried to execute macroop directly!");
         return NoFault;
@@ -60,7 +61,7 @@ output header {{
         {}
 
         Fault
-        execute(ExecContext *, Trace::InstRecord *) const
+        execute(ExecContext *, Trace::InstRecord *) const override
         {
             panic("Tried to execute macroop directly!");
         }
@@ -89,7 +90,7 @@ def template MacroDeclare {{
             %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv _env);
 
             std::string generateDisassembly(
-                    Addr pc, const Loader::SymbolTable *symtab) const;
+                    Addr pc, const Loader::SymbolTable *symtab) const override;
         };
     }
 }};
diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa
index af2975ac5..b7e3a9c36 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -51,13 +51,14 @@ output header {{
                 GenericISA::M5DebugFault *_fault);
 
         Fault
-        execute(ExecContext *xc, Trace::InstRecord *traceData) const
+        execute(ExecContext *xc, Trace::InstRecord *traceData) const override
         {
             return fault;
         }
 
         std::string
-        generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+        generateDisassembly(Addr pc,
+                            const Loader::SymbolTable *symtab) const override
         {
             std::stringstream response;
 
@@ -78,7 +79,7 @@ output header {{
                 const char *instMnem, uint64_t setFlags,
                 GenericISA::M5DebugFault *_fault, uint8_t _cc);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index e5b15c1fc..77211623c 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -82,7 +82,7 @@ def template MicroFpOpDeclare {{
                 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, int8_t _spm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 515e69ac4..348013709 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -79,7 +79,7 @@ def template MicroLeaDeclare {{
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -229,9 +229,10 @@ def template MicroLdStOpDeclare {{
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -249,9 +250,10 @@ def template MicroLdStSplitOpDeclare {{
                 uint8_t _dataSize, uint8_t _addressSize,
                 Request::FlagsType _memFlags);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index 9333c0072..f703133b0 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -61,7 +61,7 @@ def template MicroLimmOpDeclare {{
         RegIndex foldOBit;
 
         std::string generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const;
+            const Loader::SymbolTable *symtab) const override;
 
       public:
         %(class_name)s(ExtMachInst _machInst,
@@ -69,7 +69,7 @@ def template MicroLimmOpDeclare {{
                 uint64_t setFlags, InstRegIndex _dest,
                 uint64_t _imm, uint8_t _dataSize);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 488679012..3078a69ac 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -55,7 +55,7 @@ def template MediaOpRegDeclare {{
                 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -69,7 +69,7 @@ def template MediaOpImmDeclare {{
                 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
                 uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 83a4e2255..227d1cb61 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -109,7 +109,7 @@ def template MicroRegOpDeclare {{
                 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
         override;
@@ -129,7 +129,7 @@ def template MicroRegOpImmDeclare {{
                 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
         override;
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index a57dfa7a8..22af417f8 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -50,7 +50,7 @@ output header {{
                 uint16_t _target, uint8_t _cc);
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -61,7 +61,7 @@ def template SeqOpDeclare {{
         %(class_name)s(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags, uint16_t _target, uint8_t _cc);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         X86ISA::PCState branchTarget(const X86ISA::PCState &branchPC) const
         override;
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index f5e5a7742..a7dda10cf 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -52,7 +52,7 @@ output header {{
                 uint64_t setFlags, Fault _fault, uint8_t _cc);
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 
     class MicroHalt : public X86ISA::X86MicroopBase
@@ -67,10 +67,10 @@ output header {{
         {
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -81,7 +81,7 @@ def template MicroFaultDeclare {{
         %(class_name)s(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags, Fault _fault, uint8_t _cc);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -214,7 +214,7 @@ def template MicroFenceOpDeclare {{
                 const char * instMnem,
                 uint64_t setFlags);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};