From: Michael Nolan Date: Sun, 2 Feb 2020 16:59:20 +0000 (-0500) Subject: Add FLT and FLE functionality to FPCMP X-Git-Tag: ls180-24jan2020~296 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f02b554efe2b5207e5e49fd76b96480faba2e8a;p=ieee754fpu.git Add FLT and FLE functionality to FPCMP --- diff --git a/src/ieee754/fpcmp/fpcmp.py b/src/ieee754/fpcmp/fpcmp.py index 7586d8be..9eb7f3cf 100644 --- a/src/ieee754/fpcmp/fpcmp.py +++ b/src/ieee754/fpcmp/fpcmp.py @@ -50,6 +50,15 @@ class FPCMPPipeMod(PipeModBase): m.d.comb += ab_equal.eq(a1.v == b1.v) contains_nan = Signal() m.d.comb += contains_nan.eq(a1.is_nan | b1.is_nan) + a_lt_b = Signal() + with m.If(a1.s != b1.s): + comb += a_lt_b.eq(a1.s > b1.s) + with m.Elif(a1.s == 0): + comb += a_lt_b.eq(a1.v[0:31] < b1.v[0:31]) + with m.Else(): + comb += a_lt_b.eq(a1.v[0:31] > b1.v[0:31]) + + with m.If(contains_nan): m.d.comb += z1.eq(0) @@ -57,6 +66,10 @@ class FPCMPPipeMod(PipeModBase): with m.Switch(opcode): with m.Case(0b10): comb += z1.eq(ab_equal) + with m.Case(0b00): + comb += z1.eq(a_lt_b) + with m.Case(0b01): + comb += z1.eq(a_lt_b | ab_equal) # copy the context (muxid, operator) comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/ieee754/fpcmp/test/test_fpcmp_pipe.py b/src/ieee754/fpcmp/test/test_fpcmp_pipe.py index 5fd05945..af0ce953 100644 --- a/src/ieee754/fpcmp/test/test_fpcmp_pipe.py +++ b/src/ieee754/fpcmp/test/test_fpcmp_pipe.py @@ -14,6 +14,8 @@ def fpcmp_eq(a, b): def fpcmp_lt(a, b): return Float32(a.lt(b)) +def fpcmp_le(a, b): + return Float32(a.le(b)) def test_fpcmp_eq(): dut = FPCMPMuxInOut(32, 4) @@ -25,8 +27,14 @@ def test_fpcmp_lt(): runfp(dut, 32, "test_fpcmp_lt", Float32, fpcmp_lt, n_vals=100, opcode=0b00) +def test_fpcmp_le(): + dut = FPCMPMuxInOut(32, 4) + runfp(dut, 32, "test_fpcmp_le", Float32, fpcmp_le, + n_vals=100, opcode=0b01) + if __name__ == '__main__': for i in range(50): test_fpcmp_lt() test_fpcmp_eq() + test_fpcmp_le()