From: Eric Anholt <eric@anholt.net>
Date: Mon, 18 Mar 2013 22:38:58 +0000 (-0700)
Subject: i965/gen7: Align all depth miplevels to 8 in the X direction.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f112ccf;p=mesa.git

i965/gen7: Align all depth miplevels to 8 in the X direction.

On an INTEL_DEBUG=perf piglit run on IVB, reduces the instances of "HW
workaround: blit" (the printouts from the misaligned-depth workaround
blits) from 725 to 675.

It doesn't totally eliminate the workaround blit, because we still have
problems with Y offsets that we can't fix (since texturing can only align
miplevels up to 2 or 4, not 8).

No regressions on piglit/es3conform on IVB.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 35030dfcb32..59d4bc319fe 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -77,7 +77,15 @@ intel_horizontal_texture_alignment_unit(struct intel_context *intel,
    if (format == MESA_FORMAT_S8)
       return 8;
 
-   if (intel->gen >= 7 && format == MESA_FORMAT_Z16)
+   /* The depth alignment requirements in the table above are for rendering to
+    * depth miplevels using the LOD control fields.  We don't use LOD control
+    * fields, and instead use page offsets plus intra-tile x/y offsets, which
+    * require that the low 3 bits are zero.  To reduce the number of x/y
+    * offset workaround blits we do, align the X to 8, which depth texturing
+    * can handle (sadly, it can't handle 8 in the Y direction).
+    */
+   if (intel->gen >= 7 &&
+       _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
       return 8;
 
    return 4;