From: Luke Kenneth Casson Leighton Date: Mon, 18 May 2020 03:56:29 +0000 (+0100) Subject: mass-rename of modules to soc.fu.* X-Git-Tag: div_pipeline~1092 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f1344bfd96a7c0bad7664d088342e64924628f9;p=soc.git mass-rename of modules to soc.fu.* --- diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py index 347ab7d4..53e1dc36 100644 --- a/src/soc/fu/alu/formal/proof_input_stage.py +++ b/src/soc/fu/alu/formal/proof_input_stage.py @@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.input_stage import ALUInputStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.input_stage import ALUInputStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index f102fc2b..601a4875 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.main_stage import ALUMainStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.main_stage import ALUMainStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index 288da071..9e33f148 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.output_stage import ALUOutputStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.output_stage import ALUOutputStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/alu/input_stage.py b/src/soc/fu/alu/input_stage.py index 75207324..fd3fd1ed 100644 --- a/src/soc/fu/alu/input_stage.py +++ b/src/soc/fu/alu/input_stage.py @@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed, unsigned) from nmutil.pipemodbase import PipeModBase from soc.decoder.power_enums import InternalOp -from soc.alu.pipe_data import ALUInputData +from soc.fu.alu.pipe_data import ALUInputData from soc.decoder.power_enums import CryIn diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index 51001663..dd03b786 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -5,7 +5,7 @@ # output stage from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase -from soc.alu.pipe_data import ALUInputData, ALUOutputData +from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 12537957..c93fec5b 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -3,7 +3,7 @@ # register from nmigen import (Module, Signal, Cat, Repl) from nmutil.pipemodbase import PipeModBase -from soc.alu.pipe_data import ALUInputData, ALUOutputData +from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index c386397a..7c91349a 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from nmutil.dynamicpipe import SimpleHandshakeRedir -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.alu_input_record import CompALUOpSubset from ieee754.fpcommon.getop import FPPipeContext diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py index e8dd1991..3a065b2e 100644 --- a/src/soc/fu/alu/pipeline.py +++ b/src/soc/fu/alu/pipeline.py @@ -1,8 +1,8 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain -from soc.alu.input_stage import ALUInputStage -from soc.alu.main_stage import ALUMainStage -from soc.alu.output_stage import ALUOutputStage +from soc.fu.alu.input_stage import ALUInputStage +from soc.fu.alu.main_stage import ALUMainStage +from soc.fu.alu.output_stage import ALUOutputStage class ALUStages(PipeModBaseChain): def get_chain(self): diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index f42112e1..138ad3e1 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -12,9 +12,9 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA -from soc.alu.pipeline import ALUBasePipe -from soc.alu.alu_input_record import CompALUOpSubset -from soc.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.pipeline import ALUBasePipe +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.pipe_data import ALUPipeSpec import random class TestCase: diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py index fb097c87..3ac3ac89 100644 --- a/src/soc/fu/branch/formal/proof_input_stage.py +++ b/src/soc/fu/branch/formal/proof_input_stage.py @@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.input_stage import ALUInputStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.branch.br_input_record import CompBROpSubset +from soc.fu.alu.input_stage import ALUInputStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.branch.br_input_record import CompBROpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index 5ca9481d..804643df 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.logical.main_stage import LogicalMainStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.logical.main_stage import LogicalMainStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/branch/input_stage.py b/src/soc/fu/branch/input_stage.py index e6ab48ea..e0f1b34b 100644 --- a/src/soc/fu/branch/input_stage.py +++ b/src/soc/fu/branch/input_stage.py @@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed, unsigned) from nmutil.pipemodbase import PipeModBase from soc.decoder.power_enums import InternalOp -from soc.alu.pipe_data import ALUInputData +from soc.fu.alu.pipe_data import ALUInputData from soc.decoder.power_enums import CryIn diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index 6f6d488a..76b00ea0 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -7,7 +7,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase -from soc.branch.pipe_data import BranchInputData, BranchOutputData +from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData from soc.decoder.power_enums import InternalOp from soc.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 0ef4f000..43852e05 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -32,7 +32,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data -from soc.alu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import IntegerData class BranchInputData(IntegerData): diff --git a/src/soc/fu/branch/pipeline.py b/src/soc/fu/branch/pipeline.py index ac132f74..545b3435 100644 --- a/src/soc/fu/branch/pipeline.py +++ b/src/soc/fu/branch/pipeline.py @@ -1,6 +1,6 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain -from soc.branch.main_stage import BranchMainStage +from soc.fu.branch.main_stage import BranchMainStage class BranchStages(PipeModBaseChain): def get_chain(self): diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 10d2bba2..898afa8d 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -12,9 +12,9 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA -from soc.branch.pipeline import BranchBasePipe -from soc.branch.br_input_record import CompBROpSubset -from soc.alu.pipe_data import ALUPipeSpec +from soc.fu.branch.pipeline import BranchBasePipe +from soc.fu.branch.br_input_record import CompBROpSubset +from soc.fu.alu.pipe_data import ALUPipeSpec import random diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 67bd78ed..27d30731 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -11,7 +11,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase -from soc.cr.pipe_data import CRInputData, CROutputData +from soc.fu.cr.pipe_data import CRInputData, CROutputData from soc.decoder.power_enums import InternalOp from soc.decoder.power_fields import DecodeFields diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index d56c8f3f..107a340e 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.alu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import IntegerData class CRInputData(IntegerData): diff --git a/src/soc/fu/cr/pipeline.py b/src/soc/fu/cr/pipeline.py index 121cdf8d..050d0244 100644 --- a/src/soc/fu/cr/pipeline.py +++ b/src/soc/fu/cr/pipeline.py @@ -1,6 +1,6 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain -from soc.cr.main_stage import CRMainStage +from soc.fu.cr.main_stage import CRMainStage class CRStages(PipeModBaseChain): def get_chain(self): diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index fa08fb66..0ee5977d 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -12,9 +12,9 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA -from soc.cr.pipeline import CRBasePipe -from soc.alu.alu_input_record import CompALUOpSubset -from soc.alu.pipe_data import ALUPipeSpec +from soc.fu.cr.pipeline import CRBasePipe +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.pipe_data import ALUPipeSpec import random diff --git a/src/soc/fu/logical/formal/proof_bperm.py b/src/soc/fu/logical/formal/proof_bperm.py index da198940..02d63cb8 100644 --- a/src/soc/fu/logical/formal/proof_bperm.py +++ b/src/soc/fu/logical/formal/proof_bperm.py @@ -7,7 +7,7 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.logical.bperm import Bpermd +from soc.fu.logical.bperm import Bpermd import unittest diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py index bb62fb67..dedf33f6 100644 --- a/src/soc/fu/logical/formal/proof_input_stage.py +++ b/src/soc/fu/logical/formal/proof_input_stage.py @@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.input_stage import ALUInputStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.input_stage import ALUInputStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index 5ca9481d..804643df 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.logical.main_stage import LogicalMainStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.logical.main_stage import LogicalMainStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/logical/input_stage.py b/src/soc/fu/logical/input_stage.py index e6ab48ea..e0f1b34b 100644 --- a/src/soc/fu/logical/input_stage.py +++ b/src/soc/fu/logical/input_stage.py @@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed, unsigned) from nmutil.pipemodbase import PipeModBase from soc.decoder.power_enums import InternalOp -from soc.alu.pipe_data import ALUInputData +from soc.fu.alu.pipe_data import ALUInputData from soc.decoder.power_enums import CryIn diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index e740d07a..39c2400d 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -7,8 +7,8 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase -from soc.logical.pipe_data import ALUInputData -from soc.alu.pipe_data import ALUOutputData +from soc.fu.logical.pipe_data import ALUInputData +from soc.fu.alu.pipe_data import ALUOutputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp from soc.countzero.countzero import ZeroCounter diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 4bf064fe..65233fde 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.alu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import IntegerData class ALUInputData(IntegerData): diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py index f3c83276..1a2fd1fc 100644 --- a/src/soc/fu/logical/pipeline.py +++ b/src/soc/fu/logical/pipeline.py @@ -1,8 +1,8 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain -from soc.alu.input_stage import ALUInputStage -from soc.logical.main_stage import LogicalMainStage -from soc.alu.output_stage import ALUOutputStage +from soc.fu.alu.input_stage import ALUInputStage +from soc.fu.logical.main_stage import LogicalMainStage +from soc.fu.alu.output_stage import ALUOutputStage class LogicalStages(PipeModBaseChain): def get_chain(self): diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 79c1e291..d414997e 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -12,9 +12,9 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA -from soc.logical.pipeline import LogicalBasePipe -from soc.alu.alu_input_record import CompALUOpSubset -from soc.alu.pipe_data import ALUPipeSpec +from soc.fu.logical.pipeline import LogicalBasePipe +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.pipe_data import ALUPipeSpec import random diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 50264d5c..d390c501 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.shift_rot.main_stage import ShiftRotMainStage -from soc.alu.pipe_data import ALUPipeSpec -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.shift_rot.main_stage import ShiftRotMainStage +from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.decoder.power_enums import InternalOp import unittest diff --git a/src/soc/fu/shift_rot/input_stage.py b/src/soc/fu/shift_rot/input_stage.py index 72e4c925..dde41296 100644 --- a/src/soc/fu/shift_rot/input_stage.py +++ b/src/soc/fu/shift_rot/input_stage.py @@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed, unsigned) from nmutil.pipemodbase import PipeModBase from soc.decoder.power_enums import InternalOp -from soc.shift_rot.pipe_data import ShiftRotInputData +from soc.fu.shift_rot.pipe_data import ShiftRotInputData from soc.decoder.power_enums import CryIn diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index f2375283..a837fb8a 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -4,11 +4,11 @@ # output stage from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase -from soc.alu.pipe_data import ALUOutputData -from soc.shift_rot.pipe_data import ShiftRotInputData +from soc.fu.alu.pipe_data import ALUOutputData +from soc.fu.shift_rot.pipe_data import ShiftRotInputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp -from soc.shift_rot.rotator import Rotator +from soc.fu.shift_rot.rotator import Rotator from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 7f98d16b..42b70db6 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -1,8 +1,8 @@ from nmigen import Signal, Const from nmutil.dynamicpipe import SimpleHandshakeRedir -from soc.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.alu_input_record import CompALUOpSubset from ieee754.fpcommon.getop import FPPipeContext -from soc.alu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import IntegerData class ShiftRotInputData(IntegerData): diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py index 1080aa8d..316fb832 100644 --- a/src/soc/fu/shift_rot/pipeline.py +++ b/src/soc/fu/shift_rot/pipeline.py @@ -1,8 +1,8 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain -from soc.shift_rot.input_stage import ShiftRotInputStage -from soc.shift_rot.main_stage import ShiftRotMainStage -from soc.alu.output_stage import ALUOutputStage +from soc.fu.shift_rot.input_stage import ShiftRotInputStage +from soc.fu.shift_rot.main_stage import ShiftRotMainStage +from soc.fu.alu.output_stage import ALUOutputStage class ShiftRotStages(PipeModBaseChain): def get_chain(self): diff --git a/src/soc/fu/shift_rot/rotator.py b/src/soc/fu/shift_rot/rotator.py index 23aa0e43..3079a5c7 100644 --- a/src/soc/fu/shift_rot/rotator.py +++ b/src/soc/fu/shift_rot/rotator.py @@ -3,7 +3,7 @@ from nmigen import (Elaboratable, Signal, Module, Const, Cat, unsigned, signed) -from soc.shift_rot.rotl import ROTL +from soc.fu.shift_rot.rotl import ROTL # note BE bit numbering def right_mask(m, mask_begin): diff --git a/src/soc/fu/shift_rot/test/test_maskgen.py b/src/soc/fu/shift_rot/test/test_maskgen.py index 1a4d34e6..93f38f24 100644 --- a/src/soc/fu/shift_rot/test/test_maskgen.py +++ b/src/soc/fu/shift_rot/test/test_maskgen.py @@ -2,7 +2,7 @@ from nmigen import Signal, Module from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase from nmigen.cli import rtlil -from soc.alu.maskgen import MaskGen +from soc.fu.alu.maskgen import MaskGen from soc.decoder.helpers import MASK import random import unittest diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index dbd40923..def0256c 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -12,9 +12,9 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA -from soc.shift_rot.pipeline import ShiftRotBasePipe -from soc.alu.alu_input_record import CompALUOpSubset -from soc.alu.pipe_data import ALUPipeSpec +from soc.fu.shift_rot.pipeline import ShiftRotBasePipe +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.alu.pipe_data import ALUPipeSpec import random class TestCase: