From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 3 Jul 2019 09:25:05 +0000 (+0200)
Subject: Fix tests/various/specify.v
X-Git-Tag: working-ls180~1225^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f173210ebbf2cd5b5714e351ed40b6141d90b14;p=yosys.git

Fix tests/various/specify.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 73a59eb7a..5d44d78f7 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,9 +7,11 @@ module test (
 		if (EN) Q <= D;
 
 	specify
+`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
 		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
+`endif
 	endspecify
 endmodule
 
@@ -31,14 +33,7 @@ endmodule
 
 module issue01144(input clk, d, output q);
 specify
-  // Fails:
   (posedge clk => (q +: d)) = (3,1);
-  //(/*posedge*/ clk => (q +: d)) = (3,1); // Invalid syntax
   (posedge clk *> (q +: d)) = (3,1);
-  //(/*posedge*/ clk *> (q +: d)) = (3,1); // Invalid syntax
-
-  // Works:
-  (/*posedge*/ clk => q) = (3,1);
-  (/*posedge*/ clk *> q) = (3,1);
 endspecify
 endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a2b6038e4..00597e1e2 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,4 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog specify.v
+read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v