From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 13:55:22 +0000 (+0200)
Subject: litesata: pep8 (E265)
X-Git-Tag: 24jan2021_ls180~2331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f19e6ae92d1d4cbcf242b49cc5913a1fdb40204;p=litex.git

litesata: pep8 (E265)
---

diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py
index 92e59ca3..bb4aa533 100644
--- a/misoclib/mem/litesata/common.py
+++ b/misoclib/mem/litesata/common.py
@@ -321,7 +321,8 @@ class PacketBuffer(Module):
         self.sink = sink = Sink(description)
         self.source = source = Source(description)
 
-        ###
+        # # #
+
         sink_status = EndpointPacketStatus(self.sink)
         source_status = EndpointPacketStatus(self.source)
         self.submodules += sink_status, source_status
diff --git a/misoclib/mem/litesata/core/command/__init__.py b/misoclib/mem/litesata/core/command/__init__.py
index 81ecc31e..3af25fa4 100644
--- a/misoclib/mem/litesata/core/command/__init__.py
+++ b/misoclib/mem/litesata/core/command/__init__.py
@@ -19,7 +19,7 @@ class LiteSATACommandTX(Module):
         self.to_rx = to_rx = Source(tx_to_rx)
         self.from_rx = from_rx = Sink(rx_to_tx)
 
-        ###
+        # # #
 
         self.comb += [
             transport.sink.pm_port.eq(0),
@@ -124,7 +124,7 @@ class LiteSATACommandRX(Module):
         self.to_tx = to_tx = Source(rx_to_tx)
         self.from_tx = from_tx = Sink(tx_to_rx)
 
-        ###
+        # # #
 
         def test_type(name):
             return transport.source.type == fis_types[name]
diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py
index 94fea63d..e8a8ca5e 100644
--- a/misoclib/mem/litesata/core/link/__init__.py
+++ b/misoclib/mem/litesata/core/link/__init__.py
@@ -15,7 +15,7 @@ class LiteSATALinkTX(Module):
         self.sink = Sink(link_description(32))
         self.from_rx = Sink(from_rx)
 
-        ###
+        # # #
 
         self.fsm = fsm = FSM(reset_state="IDLE")
         self.submodules += fsm
@@ -117,7 +117,7 @@ class LiteSATALinkRX(Module):
         self.hold = Signal()
         self.to_tx = Source(from_rx)
 
-        ###
+        # # #
 
         self.fsm = fsm = FSM(reset_state="IDLE")
         self.submodules += fsm
diff --git a/misoclib/mem/litesata/core/link/cont.py b/misoclib/mem/litesata/core/link/cont.py
index 6a62193f..341b427b 100644
--- a/misoclib/mem/litesata/core/link/cont.py
+++ b/misoclib/mem/litesata/core/link/cont.py
@@ -7,7 +7,7 @@ class LiteSATACONTInserter(Module):
         self.sink = sink = Sink(description)
         self.source = source = Source(description)
 
-        ###
+        # # #
 
         counter = Counter(max=4)
         self.submodules += counter
@@ -79,7 +79,7 @@ class LiteSATACONTRemover(Module):
         self.sink = sink = Sink(description)
         self.source = source = Source(description)
 
-        ###
+        # # #
 
         is_data = Signal()
         is_cont = Signal()
diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py
index b72f739f..8600cf99 100644
--- a/misoclib/mem/litesata/core/link/crc.py
+++ b/misoclib/mem/litesata/core/link/crc.py
@@ -29,7 +29,7 @@ class CRCEngine(Module):
         self.last = Signal(width)
         self.next = Signal(width)
 
-        ###
+        # # #
 
         def _optimize_eq(l):
             """
@@ -93,7 +93,7 @@ class LiteSATACRC(Module):
         self.value = Signal(self.width)
         self.error = Signal()
 
-        ###
+        # # #
 
         engine = CRCEngine(self.width, self.polynom)
         self.submodules += engine
@@ -130,7 +130,7 @@ class CRCInserter(Module):
         self.source = source = Source(layout)
         self.busy = Signal()
 
-        ###
+        # # #
 
         dw = flen(sink.d)
         crc = crc_class(dw)
@@ -206,7 +206,7 @@ class CRCChecker(Module):
         self.source = source = Source(layout)
         self.busy = Signal()
 
-        ###
+        # # #
 
         dw = flen(sink.d)
         crc = crc_class(dw)
diff --git a/misoclib/mem/litesata/core/link/scrambler.py b/misoclib/mem/litesata/core/link/scrambler.py
index 948c5379..68dbd53c 100644
--- a/misoclib/mem/litesata/core/link/scrambler.py
+++ b/misoclib/mem/litesata/core/link/scrambler.py
@@ -15,7 +15,7 @@ class Scrambler(Module):
     def __init__(self):
         self.value = Signal(32)
 
-        ###
+        # # #
 
         context = Signal(16, reset=0xf0f6)
         next_value = Signal(32)
@@ -72,7 +72,7 @@ class LiteSATAScrambler(Module):
         self.sink = sink = Sink(description)
         self.source = source = Source(description)
 
-        ###
+        # # #
 
         scrambler = Scrambler()
         self.submodules += scrambler
diff --git a/misoclib/mem/litesata/core/transport/__init__.py b/misoclib/mem/litesata/core/transport/__init__.py
index 7d267de3..4375f6c1 100644
--- a/misoclib/mem/litesata/core/transport/__init__.py
+++ b/misoclib/mem/litesata/core/transport/__init__.py
@@ -29,7 +29,7 @@ class LiteSATATransportTX(Module):
     def __init__(self, link):
         self.sink = sink = Sink(transport_tx_description(32))
 
-        ###
+        # # #
 
         cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len)
         encoded_cmd = Signal(cmd_ndwords*32)
@@ -133,7 +133,7 @@ class LiteSATATransportRX(Module):
     def __init__(self, link):
         self.source = source = Source(transport_rx_description(32))
 
-        ###
+        # # #
 
         cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len,
                           fis_pio_setup_d2h_cmd_len, fis_data_cmd_len)
diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py
index 019e736a..2b27206c 100644
--- a/misoclib/mem/litesata/example_designs/test/bist.py
+++ b/misoclib/mem/litesata/example_designs/test/bist.py
@@ -151,7 +151,7 @@ if __name__ == "__main__":
     args = _get_args()
     wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     wb.open()
-    ###
+    # # #
     identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
     generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
     checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
@@ -204,5 +204,5 @@ if __name__ == "__main__":
 
         except KeyboardInterrupt:
             pass
-    ###
+    # # #
     wb.close()
diff --git a/misoclib/mem/litesata/example_designs/test/test_la.py b/misoclib/mem/litesata/example_designs/test/test_la.py
index 13095986..2b6eb57e 100644
--- a/misoclib/mem/litesata/example_designs/test/test_la.py
+++ b/misoclib/mem/litesata/example_designs/test/test_la.py
@@ -11,8 +11,7 @@ def main(wb):
     checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
     wb.open()
     regs = wb.regs
-    ###
-
+    # # #
     trig = "now"
     if len(sys.argv) < 2:
         print("No trigger condition, triggering immediately!")
@@ -60,7 +59,7 @@ def main(wb):
 
     la.upload()
     la.save("dump.vcd")
-    ###
+    # # #
     wb.close()
 
     f = open("dump_link.txt", "w")
diff --git a/misoclib/mem/litesata/example_designs/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py
index 1f29e49b..21deed9d 100644
--- a/misoclib/mem/litesata/example_designs/test/test_regs.py
+++ b/misoclib/mem/litesata/example_designs/test/test_regs.py
@@ -1,9 +1,9 @@
 def main(wb):
     wb.open()
     regs = wb.regs
-    ###
+    # # #
     print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
     print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
     print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
-    ###
+    # # #
     wb.close()
diff --git a/misoclib/mem/litesata/frontend/bist.py b/misoclib/mem/litesata/frontend/bist.py
index 6924a1bb..4655cf01 100644
--- a/misoclib/mem/litesata/frontend/bist.py
+++ b/misoclib/mem/litesata/frontend/bist.py
@@ -15,7 +15,7 @@ class LiteSATABISTGenerator(Module):
         self.aborted = Signal()
         self.errors = Signal(32)  # Note: Not used for writes
 
-        ###
+        # # #
 
         source, sink = user_port.sink, user_port.source
 
@@ -79,7 +79,7 @@ class LiteSATABISTChecker(Module):
         self.aborted = Signal()
         self.errors = Signal(32)
 
-        ###
+        # # #
 
         source, sink = user_port.sink, user_port.source
 
@@ -163,7 +163,7 @@ class LiteSATABISTUnitCSR(Module, AutoCSR):
         self._errors = CSRStatus(32)
         self._cycles = CSRStatus(32)
 
-        ###
+        # # #
 
         self.submodules += bist_unit
 
@@ -226,7 +226,7 @@ class LiteSATABISTIdentify(Module):
         self.submodules += fifo
         self.source = fifo.source
 
-        ###
+        # # #
 
         source, sink = user_port.sink, user_port.source
 
@@ -274,7 +274,7 @@ class LiteSATABISTIdentifyCSR(Module, AutoCSR):
         self._source_ack = CSR()
         self._source_data = CSRStatus(32)
 
-        ###
+        # # #
 
         self.submodules += bist_identify
         self.comb += [
diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py
index 71906700..fa9080d3 100644
--- a/misoclib/mem/litesata/phy/ctrl.py
+++ b/misoclib/mem/litesata/phy/ctrl.py
@@ -13,7 +13,8 @@ class LiteSATAPHYCtrl(Module):
         self.sink = sink = Sink(phy_description(32))
         self.source = source = Source(phy_description(32))
 
-        ###
+        # # #
+
         self.comb += [
             source.stb.eq(1),
             sink.ack.eq(1)
diff --git a/misoclib/mem/litesata/phy/datapath.py b/misoclib/mem/litesata/phy/datapath.py
index 0a3a928d..aad7614b 100644
--- a/misoclib/mem/litesata/phy/datapath.py
+++ b/misoclib/mem/litesata/phy/datapath.py
@@ -6,7 +6,7 @@ class LiteSATAPHYDatapathRX(Module):
         self.sink = sink = Sink(phy_description(16))
         self.source = source = Source(phy_description(32))
 
-        ###
+        # # #
 
     # width convertion (16 to 32) and byte alignment
         byte_alignment = Signal()
@@ -57,7 +57,7 @@ class LiteSATAPHYDatapathTX(Module):
         self.sink = sink = Sink(phy_description(32))
         self.source = source = Source(phy_description(16))
 
-        ###
+        # # #
 
     # clock domain crossing
         # (sata_gen3) sys_clk to 300MHz sata_tx clk
@@ -85,7 +85,7 @@ class LiteSATAPHYAlignInserter(Module):
         self.sink = sink = Sink(phy_description(32))
         self.source = source = Source(phy_description(32))
 
-        ###
+        # # #
 
         # send 2 ALIGN every 256 DWORDs
         # used for clock compensation between
@@ -119,7 +119,7 @@ class LiteSATAPHYAlignRemover(Module):
         self.sink = sink = Sink(phy_description(32))
         self.source = source = Source(phy_description(32))
 
-        ###
+        # # #
 
         charisk_match = sink.charisk == 0b0001
         data_match = sink.data == primitives["ALIGN"]
@@ -137,7 +137,7 @@ class LiteSATAPHYDatapath(Module):
         self.sink = sink = Sink(phy_description(32))
         self.source = source = Source(phy_description(32))
 
-        ###
+        # # #
 
     # TX path
         align_inserter = LiteSATAPHYAlignInserter(ctrl)
diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py
index deae5d1b..6e3fbc57 100644
--- a/misoclib/mem/litesata/phy/k7/trx.py
+++ b/misoclib/mem/litesata/phy/k7/trx.py
@@ -351,7 +351,7 @@ class K7LiteSATAPHYTRX(Module):
                     "p_RX_DDI_SEL": 0,
                     "p_RX_DEFER_RESET_BUF_EN": "TRUE",
 
-                #CDR Attributes
+                # CDR Attributes
                     "p_RXCDR_CFG": rxcdr_cfg,
                     "p_RXCDR_FR_RESET_ON_EIDLE": 0,
                     "p_RXCDR_HOLD_DURING_EIDLE": 0,
diff --git a/misoclib/mem/litesata/test/common.py b/misoclib/mem/litesata/test/common.py
index 6472b97d..6ecbba82 100644
--- a/misoclib/mem/litesata/test/common.py
+++ b/misoclib/mem/litesata/test/common.py
@@ -42,7 +42,9 @@ def randn(max_n):
 class PacketStreamer(Module):
     def __init__(self, description, packet_class):
         self.source = Source(description)
-        ###
+
+        # # #
+
         self.packets = []
         self.packet = packet_class()
         self.packet.done = 1
@@ -89,7 +91,9 @@ class PacketStreamer(Module):
 class PacketLogger(Module):
     def __init__(self, description, packet_class):
         self.sink = Sink(description)
-        ###
+
+        # # #
+
         self.packet_class = packet_class
         self.packet = packet_class()
 
diff --git a/misoclib/mem/litesata/test/cont_tb.py b/misoclib/mem/litesata/test/cont_tb.py
index e0fd614d..6dae6384 100644
--- a/misoclib/mem/litesata/test/cont_tb.py
+++ b/misoclib/mem/litesata/test/cont_tb.py
@@ -88,7 +88,7 @@ class TB(Module):
         yield from self.streamer.send(streamer_packet)
         yield from self.logger.receive(len(test_packet))
         #for d in self.logger.packet:
-        #    print("%08x" %d)
+        #    print("{:08}".format(d))
 
         # check results
         s, l, e = check(streamer_packet, self.logger.packet)
diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py
index e75bbff0..06cb9a2a 100644
--- a/misoclib/mem/litesata/test/hdd.py
+++ b/misoclib/mem/litesata/test/hdd.py
@@ -24,7 +24,9 @@ class PHYDword:
 class PHYSource(Module):
     def __init__(self):
         self.source = Source(phy_description(32))
-        ###
+
+        # # #
+
         self.dword = PHYDword()
 
     def send(self, dword):
@@ -42,7 +44,9 @@ class PHYSource(Module):
 class PHYSink(Module):
     def __init__(self):
         self.sink = Sink(phy_description(32))
-        ###
+
+        # # #
+
         self.dword = PHYDword()
 
     def receive(self):
@@ -462,7 +466,6 @@ class HDD(Module):
             transport_debug=False, transport_loopback=False,
             hdd_debug=False,
             ):
-        ###
         self.submodules.phy = PHYLayer()
         self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
         self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)