From: Iago Toral Quiroga <itoral@igalia.com>
Date: Wed, 4 Jan 2017 08:06:06 +0000 (+0100)
Subject: i965: get rid of brw->can_do_pipelined_register_writes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f1b8def48f5e4015d15e6cde42b1b7705459f17;p=mesa.git

i965: get rid of brw->can_do_pipelined_register_writes

Instead, check the screen field directly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 6b390b71f49..3f3da7d2009 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -983,8 +983,6 @@ brwCreateContext(gl_api api,
 
    brw->must_use_separate_stencil = devinfo->must_use_separate_stencil;
    brw->has_swizzling = screen->hw_has_swizzling;
-   brw->can_do_pipelined_register_writes =
-      screen->hw_has_pipelined_register & HW_HAS_PIPELINED_SOL_OFFSET;
 
    isl_device_init(&brw->isl_dev, devinfo, screen->hw_has_swizzling);
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 17b4256880e..113974badc8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -830,11 +830,6 @@ struct brw_context
    bool use_rep_send;
    bool use_resource_streamer;
 
-   /**
-    * Whether LRI can be used to write register values from the batch buffer.
-    */
-   bool can_do_pipelined_register_writes;
-
    /**
     * Some versions of Gen hardware don't do centroid interpolation correctly
     * on unlit pixels, causing incorrect values for derivatives near triangle
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index e746b995c1e..85f8e467f69 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -229,7 +229,7 @@ emit_l3_state(struct brw_context *brw)
    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
                                small_dw_threshold : large_dw_threshold);
 
-   if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
+   if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) {
       const struct gen_l3_config *const cfg =
          gen_get_l3_config(&brw->screen->devinfo, w);
 
@@ -296,7 +296,8 @@ gen7_restore_default_l3_config(struct brw_context *brw)
    const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
 
-   if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
+   if (cfg != brw->l3.config &&
+       can_do_pipelined_register_writes(brw->screen)) {
       setup_l3_config(brw, cfg);
       update_urb_size(brw, cfg);
       brw->l3.config = cfg;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 17fbc37c1dd..8e67b5755a7 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -219,7 +219,7 @@ intelInitExtensions(struct gl_context *ctx)
       if (brw->is_haswell)
          ctx->Extensions.ARB_gpu_shader_fp64 = true;
 
-      if (brw->can_do_pipelined_register_writes) {
+      if (can_do_pipelined_register_writes(brw->screen)) {
          ctx->Extensions.ARB_draw_indirect = true;
          ctx->Extensions.ARB_transform_feedback2 = true;
          ctx->Extensions.ARB_transform_feedback3 = true;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index 62fde036269..2cbff14f306 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -127,4 +127,10 @@ void aub_dump_bmp(struct gl_context *ctx);
 const int*
 intel_supported_msaa_modes(const struct intel_screen  *screen);
 
+static inline bool
+can_do_pipelined_register_writes(const struct intel_screen *screen)
+{
+   return screen->hw_has_pipelined_register & HW_HAS_PIPELINED_SOL_OFFSET;
+}
+
 #endif