From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Feb 2019 13:41:34 +0000 (+0100)
Subject: Merge pull request #802 from whitequark/write_verilog_async_mem_ports
X-Git-Tag: yosys-0.9~316
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f2548a564812d55b8263020d5fe9e92368f818e;p=yosys.git

Merge pull request #802 from whitequark/write_verilog_async_mem_ports

write_verilog: correctly emit asynchronous transparent ports
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1f2548a564812d55b8263020d5fe9e92368f818e