From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 21 Jul 2020 17:54:42 +0000 (+0200)
Subject: soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing.
X-Git-Tag: 24jan2021_ls180~68
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f27b7405e260fe5c57374e95e7040440bf11fbc;p=litex.git

soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing.
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index e7d2886d..f258bbc0 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1299,7 +1299,10 @@ class LiteXSoC(SoC):
             bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
             self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
             self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
-            self.bus.add_master("sdblock2mem", master=bus)
+            if hasattr(self.cpu, "dmabus"): # FIXME: VexRiscv SMP / DMA test.
+                self.submodules += wishbone.Converter(bus, self.cpu.dmabus)
+            else:
+                self.bus.add_master("sdblock2mem", master=bus)
             self.add_csr("sdblock2mem")
 
         # Mem2Block DMA