From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Mar 2019 15:46:13 +0000 (+0000)
Subject: try sync with o_mid
X-Git-Tag: ls180-24jan2020~1494
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f3d67f1228d00d58acfc7a3395857232724495f;p=ieee754fpu.git

try sync with o_mid
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 97ee057b..cecb50d6 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -581,6 +581,7 @@ class UnbufferedPipeline(PipelineBase):
 
         if self.p_mux:
             mid = self.p_mux.m_id
+            o_mid = Signal(len(mid))
             for i in range(p_len):
                 m.d.sync += data_valid[i].eq(0)
                 m.d.comb += n_i_readyn[i].eq(1)
@@ -599,13 +600,14 @@ class UnbufferedPipeline(PipelineBase):
             m.d.comb += self.n[ni].o_valid.eq(anyvalid.bool())
             m.d.sync += data_valid[mid].eq(p_i_valid[mid] | \
                                         (n_i_readyn[mid] & data_valid[mid]))
+            m.d.sync += eq(o_mid, mid)
 
             for i in range(p_len):
                 with m.If(self.p[i].i_valid & self.p[i].o_ready):
                     m.d.sync += eq(r_data[i], self.p[i].i_data)
 
             m.d.comb += eq(self.n[ni].o_data,
-                           self.stage.process(r_data[mid]))
+                           self.stage.process(r_data[o_mid]))
         else:
             for i in range(p_len):
                 m.d.comb += p_i_valid[i].eq(self.p[i].i_valid_logic())