From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 May 2020 00:02:21 +0000 (+0100)
Subject: remove operand c from ALU in/out
X-Git-Tag: div_pipeline~1267
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f4e011781130dd5646b722dbffe410f730a7a67;p=soc.git

remove operand c from ALU in/out
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index e3511eec..e6ab48ea 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -44,10 +44,6 @@ class ALUInputStage(PipeModBase):
         # If there's an immediate, set the B operand to that
         comb += self.o.b.eq(self.i.b)
 
-        ##### operand C? #####
-
-        comb += self.o.c.eq(self.i.c)
-
         ##### carry-in #####
 
         # either copy incoming carry or set to 1/0 as defined by op
diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index f64a39f9..13be9747 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -22,7 +22,6 @@ class ALUInputData(IntegerData):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
         self.b = Signal(64, reset_less=True) # RB/immediate
-        self.c = Signal(64, reset_less=True) # RC/RS
         self.so = Signal(reset_less=True)
         self.carry_in = Signal(reset_less=True)
 
@@ -30,13 +29,12 @@ class ALUInputData(IntegerData):
         yield from super().__iter__()
         yield self.a
         yield self.b
-        yield self.c
         yield self.carry_in
         yield self.so
 
     def eq(self, i):
         lst = super().eq(i)
-        return lst + [self.a.eq(i.a), self.b.eq(i.b), self.c.eq(i.c),
+        return lst + [self.a.eq(i.a), self.b.eq(i.b),
                       self.carry_in.eq(i.carry_in),
                       self.so.eq(i.so)]