From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Mar 2019 05:38:45 +0000 (+0000)
Subject: enable single-cycle in FP16 test
X-Git-Tag: ls180-24jan2020~1744
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f54946e9b8215d0a26228722ba42f4793325901;p=ieee754fpu.git

enable single-cycle in FP16 test
---

diff --git a/src/add/test_add16.py b/src/add/test_add16.py
index 41b35f68..f39ae8ae 100644
--- a/src/add/test_add16.py
+++ b/src/add/test_add16.py
@@ -39,6 +39,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=16, single_cycle=False)
+    dut = FPADD(width=16, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")