From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jul 2019 06:00:04 +0000 (+0100)
Subject: fix min-range rounding
X-Git-Tag: ls180-24jan2020~904
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f583abd8fdf36849770557c58d169c6792ba67f;p=ieee754fpu.git

fix min-range rounding
---

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 787a4bbc..378855a0 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -73,6 +73,10 @@ class FPCVTSpecialCasesMod(Elaboratable):
         z1 = self.o.z
         print ("z1", z1.width, z1.rmw, z1.e_width, z1.e_start, z1.e_end)
 
+        me = a1.rmw
+        ms = a1.rmw - self.o.z.rmw
+        print ("ms-me", ms, me)
+
         # intermediaries
         exp_sub_n126 = Signal((a1.e_width, True), reset_less=True)
         exp_gt127 = Signal(reset_less=True)
@@ -89,17 +93,17 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # if a range outside z's min range (-126)
         with m.Elif(exp_sub_n126 < 0):
-            m.d.comb += self.o.of.guard.eq(a1.m[-self.o.z.rmw-2])
-            m.d.comb += self.o.of.round_bit.eq(a1.m[-self.o.z.rmw-3])
-            m.d.comb += self.o.of.sticky.eq(a1.m[:-self.o.z.rmw-1] != 0)
-            m.d.comb += self.o.of.m0.eq(self.o.z.m[0])
+            m.d.comb += self.o.of.guard.eq(a1.m[ms-1])
+            m.d.comb += self.o.of.round_bit.eq(a1.m[ms-2])
+            m.d.comb += self.o.of.sticky.eq(a1.m[:ms-2].bool())
+            m.d.comb += self.o.of.m0.eq(a1.m[ms]) # bit of a1
 
             m.d.comb += self.o.z.s.eq(a1.s)
             m.d.comb += self.o.z.e.eq(a1.e)
             m.d.comb += self.o.z.m.eq(a1.m[-self.o.z.rmw-1:])
             m.d.comb += self.o.z.m[-1].eq(1)
 
-        # if a is inf return inf 
+        # if a is inf return inf
         with m.Elif(a1.is_inf):
             m.d.comb += self.o.z.inf(a1.s)
             m.d.comb += self.o.out_do_z.eq(1)
@@ -117,13 +121,10 @@ class FPCVTSpecialCasesMod(Elaboratable):
 
         # ok after all that, anything else should fit fine (whew)
         with m.Else():
-            me = a1.rmw
-            ms = a1.rmw - self.o.z.rmw
-            print ("ms-me", ms, me)
             m.d.comb += self.o.of.guard.eq(a1.m[ms-1])
             m.d.comb += self.o.of.round_bit.eq(a1.m[ms-2])
             m.d.comb += self.o.of.sticky.eq(a1.m[:ms-2].bool())
-            m.d.comb += self.o.of.m0.eq(a1.m[ms]) # last bit of a1 NOT z
+            m.d.comb += self.o.of.m0.eq(a1.m[ms]) # bit of a1
 
             # XXX TODO: this is basically duplicating FPRoundMod. hmmm...
             print ("alen", a1.e_start, z1.fp.N126, N126)
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 76d52ddb..30e86a36 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -137,6 +137,10 @@ class InputTestRandom(InputTest):
                     #op1 = 0xc27ff989
                     #op1 = 0x41689000
                     #op1 = 0xbbc0edec
+                    #op1 = 0x2EDBE6FF
+                    #op1 = 0x358637BD
+                    #op1 = 0x3340f2a7
+                    #op1 = 0x33D6BF95
                     vals.append((op1,))
                 else:
                     op1 = randint(0, (1<<width)-1)