From: bunnie <bunnie@kosagi.com>
Date: Fri, 24 Jan 2020 07:01:13 +0000 (+0800)
Subject: add BUFIO to clockgen buffer options
X-Git-Tag: 24jan2021_ls180~716^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f7549b4c0f7487ec5af94a32008c8c5004194a5;p=litex.git

add BUFIO to clockgen buffer options
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 3d427bcf..5e62f5de 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -59,6 +59,8 @@ class XilinxClocking(Module, AutoCSR):
                 self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
             elif buf == "bufgce" and clk_ce != None:
                 self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce)
+            elif buf == "bufio":
+                self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf)
             else:
                 raise ValueError