From: lkcl Date: Thu, 28 Apr 2022 17:13:23 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2548 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1fc2e63a01c76ac605b43767dfef708a70b6f808;p=libreriscv.git --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index c908420a8..7e0c72aa6 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -402,8 +402,8 @@ However when moving to 64-bit digits (desirable because the algorithm is `O(N^2)`) this in turn means that the estimate has to be computed from a *128* bit dividend and a 64-bit divisor. Such an operation simply does not exist in most Scalar 64-bit ISAs. Although Power ISA -comes close with `divdeu`, by placing the dividend in the upper half -of a 128-bit computation, the lower half is zero. Again Power ISA +comes close with `divdeu`, by placing one operand in the upper half +of a 128-bit dividend, the lower half is zero. Again Power ISA has a Packed SIMD instruction `vdivuq` which is a 128/128 (quad) divide, not a 128/64, and its use would require considerable effort to move registers to and from GPRs. Some investigation into