From: Florent Kermarrec Date: Fri, 24 Jul 2020 14:34:17 +0000 (+0200) Subject: targets: keep in sync with litex-boards. X-Git-Tag: 24jan2021_ls180~56 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1fdffdfd6b5d2ef6aa1330b9db1f39b2693f7045;p=litex.git targets: keep in sync with litex-boards. --- diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 30df7859..16d1d01e 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -145,47 +145,6 @@ _io = [ ), ] -_i2s_pmod_io = [ - # I2S PMOD on JD: - # - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ - ("i2s_rx_mclk", 0, Pins("E2"), IOStandard("LVCMOS33")), - ("i2s_rx", 0, - Subsignal("clk", Pins("H2")), - Subsignal("sync", Pins("D2")), - Subsignal("rx", Pins("G2")), - IOStandard("LVCMOS33"), - ), - ("i2s_tx_mclk", 0, Pins("D4"), IOStandard("LVCMOS33")), - ("i2s_tx", 0, - Subsignal("clk",Pins("F4")), - Subsignal("sync", Pins("D3")), - Subsignal("tx", Pins("F3")), - IOStandard("LVCMOS33"), - ), -] - -_sdcard_pmod_io = [ - # SDCard PMOD on JD: - # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ - # - https://github.com/antmicro/arty-expansion-board - ("spisdcard", 0, - Subsignal("clk", Pins("F3")), - Subsignal("mosi", Pins("D3"), Misc("PULLUP True")), - Subsignal("cs_n", Pins("D4"), Misc("PULLUP True")), - Subsignal("miso", Pins("F4"), Misc("PULLUP True")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS33"), - ), - ("sdcard", 0, - Subsignal("data", Pins("F4 E2 D2 D4"), Misc("PULLUP True")), - Subsignal("cmd", Pins("D3"), Misc("PULLUP True")), - Subsignal("clk", Pins("F3")), - Subsignal("cd", Pins("H2")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS33"), - ), -] - # Connectors --------------------------------------------------------------------------------------- _connectors = [ @@ -279,6 +238,64 @@ _connectors = [ } ), ] +# PMODS -------------------------------------------------------------------------------------------- + +def usb_pmod_io(pmod): + return [ + # USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/ + ("usb_uart", 0, + Subsignal("tx", Pins(f"{pmod}:1")), + Subsignal("rx", Pins(f"{pmod}:2")), + IOStandard("LVCMOS33") + ), + ] +_usb_uart_pmod_io = usb_pmod_io("pmoda") # USB-UART PMOD on JA. + + +def i2s_pmod_io(pmod): + return [ + # I2S PMOD: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ + ("i2s_rx_mclk", 0, Pins(f"{pmod}:4"), IOStandard("LVCMOS33")), + ("i2s_rx", 0, + Subsignal("clk", Pins(f"{pmod}:6")), + Subsignal("sync", Pins(f"{pmod}:5")), + Subsignal("rx", Pins(f"{pmod}:7")), + IOStandard("LVCMOS33"), + ), + ("i2s_tx_mclk", 0, Pins(f"{pmod}:0"), IOStandard("LVCMOS33")), + ("i2s_tx", 0, + Subsignal("clk",Pins(f"{pmod}:2")), + Subsignal("sync", Pins(f"{pmod}:1")), + Subsignal("tx", Pins(f"{pmod}:3")), + IOStandard("LVCMOS33"), + ), + ] +_i2s_pmod_io = i2s_pmod_io("pmodd") # I2S PMOD on JD. + +def sdcard_pmod_io(pmod): + return [ + # SDCard PMOD: + # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ + # - https://github.com/antmicro/arty-expansion-board + ("spisdcard", 0, + Subsignal("clk", Pins(f"{pmod}:3")), + Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")), + Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")), + Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), + ), + ("sdcard", 0, + Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")), + Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")), + Subsignal("clk", Pins(f"{pmod}:3")), + Subsignal("cd", Pins(f"{pmod}:6")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), + ), +] +_sdcard_pmod_io = sdcard_pmod_io("pmodd") # SDCARD PMOD on JD. + # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 01b9df6b..7eab57de 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -128,13 +128,21 @@ def main(): builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(args.toolchain, with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, **soc_sdram_argdict(args)) + assert not (args.with_spi_sdcard and args.with_sdcard) + soc.platform.add_extension(arty._sdcard_pmod_io) + if args.with_spi_sdcard: + soc.add_spi_sdcard() + if args.with_sdcard: + soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} builder.build(**builder_kwargs, run=args.build) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index b284e2a4..758fca14 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -20,14 +20,18 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litedram.modules import IS42S16160 -from litedram.phy import GENSDRPHY +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) + else: + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -38,15 +42,20 @@ class _CRG(Module): self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(50e6), **kwargs): + def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs): platform = de0nano.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -56,14 +65,15 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, "1:1"), + module = IS42S16160(sys_clk_freq, sdram_rate), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), @@ -83,11 +93,12 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 9e43ffda..8897dbda 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -16,7 +16,7 @@ from litex.build.io import DDROutput from litex.boards.platforms import minispartan6 -from litex.soc.cores.clock import * +from litex.soc.cores.clock import S6PLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -28,33 +28,37 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, clk_freq, sdram_sys2x=False): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.clock_domains.cd_sys = ClockDomain() - if sdram_sys2x: - self.clock_domains.cd_sys2x = ClockDomain() + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) else: self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # + # Clk / Rst + clk32 = platform.request("clk32") + + # PLL self.submodules.pll = pll = S6PLL(speedgrade=-1) - pll.register_clkin(platform.request("clk32"), 32e6) - pll.create_clkout(self.cd_sys, clk_freq) - if sdram_sys2x: - pll.create_clkout(self.cd_sys2x, 2*clk_freq) - pll.create_clkout(self.cd_sys2x_ps, 2*clk_freq, phase=90) + pll.register_clkin(clk32, 32e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) else: - pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - sdram_clk = ClockSignal("sys2x_ps" if sdram_sys2x else "sys_ps") + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(80e6), sdram_sys2x=False, **kwargs): + def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", **kwargs): platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -64,19 +68,15 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_sys2x=sdram_sys2x) + self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - if sdram_sys2x: - self.submodules.sdrphy = HalfRateGENSDRPHY(platform.request("sdram")) - rate = "1:2" - else: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - rate = "1:1" + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = AS4C16M16(sys_clk_freq, rate), + module = AS4C16M16(sys_clk_freq, sdram_rate), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), @@ -96,12 +96,12 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-sys2x", action="store_true", help="Use double frequency for SDRAM PHY") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(sdram_sys2x=args.sdram_sys2x, **soc_sdram_argdict(args)) + soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 98448974..76f73878 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -24,14 +24,18 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litedram import modules as litedram_modules -from litedram.phy import GENSDRPHY +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq, with_usb_pll=False): + def __init__(self, platform, sys_clk_freq, with_usb_pll=False, sdram_rate="1:1"): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) + else: + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -44,7 +48,11 @@ class _CRG(Module): self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90) + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # USB PLL @@ -57,7 +65,8 @@ class _CRG(Module): usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) # SDRAM clock - self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # Prevent ESP32 from resetting FPGA self.comb += platform.request("wifi_gpio0").eq(1) @@ -66,7 +75,7 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, device="LFE5U-45F", toolchain="trellis", - sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): + sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) @@ -78,14 +87,15 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" - self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll) + self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"), + module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), @@ -111,14 +121,16 @@ def main(): parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) args = parser.parse_args() soc = BaseSoC(device=args.device, toolchain=args.toolchain, - sys_clk_freq=int(float(args.sys_clk_freq)), - sdram_module_cls=args.sdram_module, + sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_module_cls = args.sdram_module, + sdram_rate = args.sdram_rate, **soc_sdram_argdict(args)) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: