From: Clifford Wolf Date: Sat, 21 Feb 2015 13:25:34 +0000 (+0100) Subject: YosysJS: Wait for Viz to load X-Git-Tag: yosys-0.6~405 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1fe15a5973bcd7b5d07ea82fd85545a6e73a20f0;p=yosys.git YosysJS: Wait for Viz to load --- diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html index 36cc6cf4a..c9386aee8 100644 --- a/misc/yosysjs/demo03.html +++ b/misc/yosysjs/demo03.html @@ -24,16 +24,18 @@ endmodule

YosysJS Example Application #03

Your mission: Create a behavioral Verilog model for the following circuit:

- -

-

module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
-  always @(posedge clock) begin
-    Y <= A | {4{reset}};
-  end
-endmodule

- -

-

 

+