From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 31 Jul 2018 18:26:47 +0000 (-0700)
Subject: Make sstatus.MXR readable
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb;p=riscv-isa-sim.git

Make sstatus.MXR readable

h/t @taoliug
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 52f69c1..2a4a18c 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -584,7 +584,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_MCOUNTEREN: return state.mcounteren;
     case CSR_SSTATUS: {
       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
-                 | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
+                 | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
       reg_t sstatus = state.mstatus & mask;
       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
           (sstatus & SSTATUS_XS) == SSTATUS_XS)