From: Alexandre Oliva Date: Mon, 8 Dec 2003 20:58:03 +0000 (+0000) Subject: frv.md (subdi2): Merge with _internal insn_and_split, by using match_scratch. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ff905e97f87d4fdff4c305fa2dbb10314e2ef59;p=gcc.git frv.md (subdi2): Merge with _internal insn_and_split, by using match_scratch. * config/frv/frv.md (subdi2): Merge with _internal insn_and_split, by using match_scratch. (negdi2): New. From-SVN: r74438 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f5e0a287ee3..5bbfb64832f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2003-12-08 Alexandre Oliva + + * config/frv/frv.md (subdi2): Merge with _internal insn_and_split, + by using match_scratch. + (negdi2): New. + 2003-12-08 Jason Merrill Daniel Berlin diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md index ce5ce8bac25..0748c265a62 100644 --- a/gcc/config/frv/frv.md +++ b/gcc/config/frv/frv.md @@ -2754,22 +2754,11 @@ ;; Subtraction No need to worry about constants, since the compiler ;; canonicalizes them into adddi3's. -(define_expand "subdi3" - [(parallel [(set (match_operand:DI 0 "integer_register_operand" "") - (minus:DI (match_operand:DI 1 "integer_register_operand" "") - (match_operand:DI 2 "integer_register_operand" ""))) - (clobber (match_dup 3))])] - "" - " -{ - operands[3] = gen_reg_rtx (CCmode); -}") - -(define_insn_and_split "*subdi3_internal" +(define_insn_and_split "subdi3" [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e") (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e") (match_operand:DI 2 "integer_register_operand" "e,e,0"))) - (clobber (match_operand:CC 3 "icc_operand" "=t,t,t"))] + (clobber (match_scratch:CC 3 "=t,t,t"))] "" "#" "reload_completed" @@ -2842,6 +2831,31 @@ [(set_attr "length" "4") (set_attr "type" "int")]) +(define_insn_and_split "negdi2" + [(set (match_operand:DI 0 "integer_register_operand" "=&e,e") + (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0"))) + (clobber (match_scratch:CC 2 "=t,t"))] + "" + "#" + "reload_completed" + [(match_dup 3) + (match_dup 4)] + " +{ + rtx op0_high = gen_highpart (SImode, operands[0]); + rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST); + rtx op2_high = gen_highpart (SImode, operands[1]); + rtx op0_low = gen_lowpart (SImode, operands[0]); + rtx op1_low = op1_high; + rtx op2_low = gen_lowpart (SImode, operands[1]); + rtx op3 = operands[2]; + + operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3); + operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3); +}" + [(set_attr "length" "8") + (set_attr "type" "multi")]) + ;; Multiplication (same size) ;; (define_insn "muldi3" ;; [(set (match_operand:DI 0 "register_operand" "=r")