From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 17:16:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~595
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ff9b09dd22a20485733b26f633da53400e8f520;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 323c6c105..50b3babb7 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -29,6 +29,9 @@ instruction deviate from the Scalar Power ISA Specification.
 
 Summary of Compliancy Levels, each Level includes all lower levels:
 
+* **Zero-Level**: Simple-V is not implemented (at all) in hardware. This
+  Level is required to be listed because all capabilities of Simple-V
+  must be Soft-emulatable.
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
   to/from SVSRR1. Register Files as Standard Power ISA. `scalar identity`
   implemented.
@@ -64,6 +67,16 @@ The SV Compliancy Levels have nothing to do with the Power ISA Compliancy
 Levels (SFS, SFFS, Linux, AIX). They are separate and independent. It
 is perfectly fine to implement Ultra-Embedded on AIX, and perfectly fine to implement 3D/Advanced on SFS. **Compliance with SV Levels does not convey or remove the obligation of Compliance with SFS/SFFS/Linux/AIX Levels and vice-versa**.
 
+# Zero-Level
+
+This level exists to indicate the critical importance of all and any
+features attempted to be executed on hardware that has no support at
+all for Simple-V being **required** to raise Illegal Exceptions.
+
+With parts of the Power ISA being "silent executed" (hints for example),
+it is absolutely critical to have all capabilities of Simple-V sit
+within full Illegal Instruction space of existing and future Hardware.
+
 # Ultra-Embedded Level
 
 This level exists as an entry-level into SVP64, most suited to resource