From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Oct 2022 13:20:04 +0000 (+0100)
Subject: sort out dsld pseudocode, creating mask is tricky
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ffcbeef7c072908c06c4fbdb16da3a7862517eb;p=openpower-isa.git

sort out dsld pseudocode, creating mask is tricky
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index ad528604..c1f79c0b 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -57,7 +57,8 @@ Pseudo-code:
 
     n <- (RB)[58:63]
     v <- ROTL128([0]*64 || (RA), n)
-    RT <- v[64:127] | ((RC) & MASK(n, 63))
+    mask <- ¬MASK(64, 63-n)
+    RT <- v[64:127] | ((RC) & mask)
     RS <- v[0:63]
 
 Special Registers Altered:
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index ca2247c1..ad42f80e 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1042,6 +1042,7 @@ class PowerDecodeSubset(Elaboratable):
             comb += self.implicit_rs.eq(0)
             comb += self.extend_rb_maxvl.eq(0)
             comb += self.extend_rc_maxvl.eq(0)
+            # implicit RS for major 59
             with m.If((major == 59) & xo.matches(
                     '-----00100',  # ffmsubs
                     '-----00101',  # ffmadds
@@ -1054,10 +1055,13 @@ class PowerDecodeSubset(Elaboratable):
                 comb += self.extend_rb_maxvl.eq(1) # extend RB
             xo6 = Signal(6)
             comb += xo6.eq(self.dec.opcode_in[0:6])
+            # implicit RS for major 4
             with m.If((major == 4) & xo6.matches(
                     '111000',  # pcdec
                     '110010',  # maddedu
                     '111010',  # divmod2du
+                    '11010-',  # dsld
+                    '11011-',  # dsrd
                 )):
                 comb += self.implicit_rs.eq(1)
                 comb += self.extend_rc_maxvl.eq(1) # RS=RT+MAXVL or RS=RC
diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 6a314212..21223be3 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -4,7 +4,7 @@ from openpower.test.state import ExpectedState
 from openpower.simulator.program import Program
 from openpower.decoder.isa.caller import SVP64State
 
-_SHIFT_TEST_RANGE = range(-64, 128, 16)
+_SHIFT_TEST_RANGE = list(range(-64, 128, 16)) + [1, 63]
 
 
 class BigIntCases(TestAccumulatorBase):
@@ -34,45 +34,20 @@ class BigIntCases(TestAccumulatorBase):
     # FIXME: test more divmod2du special cases
 
     def case_dsld0(self):
-        prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False)
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,6"])), False)
         for sh in _SHIFT_TEST_RANGE:
             with self.subTest(sh=sh):
                 gprs = [0] * 32
-                gprs[3] = 0x123456789ABCDEF
-                gprs[4] = 0xFEDCBA9876543210
-                gprs[5] = sh % 2 ** 64
-                e = ExpectedState(pc=4, int_regs=gprs)
-                v = (gprs[3] << 64) | gprs[4]
-                v <<= sh % 64
-                e.intregs[3] = (v >> 64) % 2 ** 64
-                self.add_case(prog, gprs, expected=e)
-
-    def case_dsld1(self):
-        prog = Program(list(SVP64Asm(["dsld 3,3,5,4"])), False)
-        for sh in _SHIFT_TEST_RANGE:
-            with self.subTest(sh=sh):
-                gprs = [0] * 32
-                gprs[3] = 0x123456789ABCDEF
+                gprs[6] = 0x123456789ABCDEF
                 gprs[4] = 0xFEDCBA9876543210
                 gprs[5] = sh % 2 ** 64
                 e = ExpectedState(pc=4, int_regs=gprs)
-                v = (gprs[4] << 64) | gprs[3]
-                v <<= sh % 64
-                e.intregs[3] = (v >> 64) % 2 ** 64
-                self.add_case(prog, gprs, expected=e)
-
-    def case_dsld2(self):
-        prog = Program(list(SVP64Asm(["dsld 3,5,3,4"])), False)
-        for sh in _SHIFT_TEST_RANGE:
-            with self.subTest(sh=sh):
-                gprs = [0] * 32
-                gprs[3] = sh % 2 ** 64
-                gprs[4] = 0xFEDCBA9876543210
-                gprs[5] = 0x02468ACE13579BDF
-                e = ExpectedState(pc=4, int_regs=gprs)
-                v = (gprs[4] << 64) | gprs[5]
+                v = gprs[4]
                 v <<= sh % 64
-                e.intregs[3] = (v >> 64) % 2 ** 64
+                mask = (1<<(sh%64))-1
+                v |= gprs[6] & mask
+                e.intregs[3] = v         % 2 ** 64
+                e.intregs[6] = (v >> 64) % 2 ** 64
                 self.add_case(prog, gprs, expected=e)
 
     def case_dsrd0(self):