From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 3 Mar 2015 23:57:37 +0000 (+0100)
Subject: uart: generate ack for rx (serialboot OK with sim)
X-Git-Tag: 24jan2021_ls180~2510^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=200791c81d9c4574d81fd746ec70e66426077300;p=litex.git

uart: generate ack for rx (serialboot OK with sim)
---

diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py
index 8d566fb6..a07462a7 100644
--- a/misoclib/com/uart/__init__.py
+++ b/misoclib/com/uart/__init__.py
@@ -26,5 +26,6 @@ class UART(Module, AutoCSR):
 		]
 		self.comb += [
 			self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
-			self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
+			self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),
+			phy.source.ack.eq(~self.ev.rx.pending)
 		]
diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
index 2879b2cb..4682a53f 100644
--- a/misoclib/com/uart/phy/sim.py
+++ b/misoclib/com/uart/phy/sim.py
@@ -12,5 +12,6 @@ class UARTPHYSim(Module):
 			self.sink.ack.eq(pads.source_ack),
 
 			self.source.stb.eq(pads.sink_stb),
-			self.source.data.eq(pads.sink_data)
+			self.source.data.eq(pads.sink_data),
+			pads.sink_ack.eq(self.source.ack)
 		]