From: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Date: Mon, 23 Sep 2019 11:45:46 +0000 (+0200)
Subject: boards/targets: increase integrated ROM size if EthernetSoC is used
X-Git-Tag: 24jan2021_ls180~993^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=201218b2c32555fc77da7b9009b1af96a602c082;p=litex.git

boards/targets: increase integrated ROM size if EthernetSoC is used

Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
---

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 4e3a0a07..bc5a6732 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -51,10 +51,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = arty.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)
 
@@ -77,7 +77,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
                                                self.platform.request("eth"))
diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index d025340e..cfa9f438 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -44,10 +44,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = genesys2.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                           **kwargs)
 
@@ -70,7 +70,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 4bb90216..ba6aab5c 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -46,10 +46,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = kc705.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                           **kwargs)
 
@@ -72,7 +72,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
                                             self.platform.request("eth"), clk_freq=self.clk_freq)
diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 04670b82..08493966 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -80,10 +80,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
         platform = kcu105.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                           **kwargs)
 
@@ -108,7 +108,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
         self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 13d69754..caa3b00e 100755
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -48,10 +48,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = netv2.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)
 
@@ -74,7 +74,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 00f07116..e24e6fb9 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -49,10 +49,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = nexys4ddr.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)
 
@@ -76,7 +76,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 6bd011ec..73f2565a 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -49,10 +49,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
         platform = nexys_video.Platform()
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                         integrated_rom_size=0x8000,
+                         integrated_rom_size=integrated_rom_size,
                          integrated_sram_size=0x8000,
                          **kwargs)
 
@@ -75,7 +75,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
+        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))
diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index f8bcd948..a1fce670 100755
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -19,10 +19,10 @@ from liteeth.mac import LiteEthMAC
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, **kwargs):
+    def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
         sys_clk_freq = int(1e9/platform.default_clk_period)
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size=0x8000,
+            integrated_rom_size=integrated_rom_size,
             integrated_main_ram_size=16*1024,
             **kwargs)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
@@ -35,7 +35,7 @@ class EthernetSoC(BaseSoC):
     }
     mem_map.update(BaseSoC.mem_map)
 
-    def __init__(self, platform, **kwargs):
+    def __init__(self, platform, integrated_rom_size=0x10000, **kwargs):
         BaseSoC.__init__(self, platform, **kwargs)
 
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 9094992f..7c4779ac 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -76,10 +76,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-                          integrated_rom_size=0x8000,
+                          integrated_rom_size=integrated_rom_size,
                           **kwargs)
 
         # crg
@@ -107,7 +107,7 @@ class EthernetSoC(BaseSoC):
     mem_map.update(BaseSoC.mem_map)
 
     def __init__(self, toolchain="diamond", **kwargs):
-        BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
+        BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYRGMII(
             self.platform.request("eth_clocks"),