From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sat, 16 Oct 2021 01:12:49 +0000 (-0700)
Subject: add WIP code for handling Slice and Cat in a unified way, supporting assignment
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2023214b7f47501995999689607977874a3915d2;p=ieee754fpu.git

add WIP code for handling Slice and Cat in a unified way, supporting assignment
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index b899397f..369d96e5 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -151,6 +151,7 @@ class SimdSignal(UserValue):
         return PRepl(self.m, self, count, self.ptype)
 
     def __Cat__(self, *args, src_loc_at=0):
+        # TODO: need SwizzledSimdValue-aware Cat
         args = [self] + list(args)
         for sig in args:
             assert isinstance(sig, SimdSignal), \
@@ -169,6 +170,10 @@ class SimdSignal(UserValue):
         # print ("partsig ass", self, val)
         return PAssign(self.m, self, val, self.ptype)
 
+    def __Slice__(self, start, stop, *, src_loc_at=0):
+        # TODO: add __Slice__ redirection to nmigen
+        raise NotImplementedError("TODO: need SwizzledSimdValue-aware Slice")
+
     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
     # def __Switch__(self, cases, *, src_loc=None, src_loc_at=0,
     #                               case_src_locs={}):