From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Tue, 12 Apr 2011 00:10:16 +0000 (-0700)
Subject: [sim] fixed FSR exception field bug
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2032e6c6b71b733550d7609f066cb02943588e56;p=riscv-isa-sim.git

[sim] fixed FSR exception field bug
---

diff --git a/riscv/decode.h b/riscv/decode.h
index cf2ee57..499181d 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -63,7 +63,7 @@ const int JUMP_ALIGN_BITS = 1;
 #define FPEXC_NX 0x01
 #define FPEXC_UF 0x02
 #define FPEXC_OF 0x04
-#define FPEXC_DZ 0x02
+#define FPEXC_DZ 0x08
 #define FPEXC_NV 0x10
 
 #define FSR_AEXC_SHIFT 0