From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 6 Dec 2006 10:51:18 +0000 (-0500)
Subject: Change how optional delay slot instructions are detected and squashed.
X-Git-Tag: m5_2.0_beta3~274^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20340b5e26e05edd364eda5f69949cc8f957921b;p=gem5.git

Change how optional delay slot instructions are detected and squashed.

--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
---

diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index aa58fc20e..4683c77af 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -87,7 +87,7 @@ struct DefaultIEWDefaultCommit {
     bool squash[Impl::MaxThreads];
     bool branchMispredict[Impl::MaxThreads];
     bool branchTaken[Impl::MaxThreads];
-    bool condDelaySlotBranch[Impl::MaxThreads];
+    bool squashDelaySlot[Impl::MaxThreads];
     uint64_t mispredPC[Impl::MaxThreads];
     uint64_t nextPC[Impl::MaxThreads];
     InstSeqNum squashedSeqNum[Impl::MaxThreads];
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e72679710..ba6a62b4d 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -728,27 +728,12 @@ DefaultCommit<Impl>::commit()
             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
 
 #if ISA_HAS_DELAY_SLOT
-            InstSeqNum bdelay_done_seq_num;
-            bool squash_bdelay_slot;
-
-            if (fromIEW->branchMispredict[tid]) {
-                if (fromIEW->branchTaken[tid] &&
-                    fromIEW->condDelaySlotBranch[tid]) {
-                    DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
-                            "mispredicted as taken. Squashing after previous "
-                            "inst, [sn:%i]\n",
-                            tid, squashed_inst);
-                     bdelay_done_seq_num = squashed_inst;
-                     squash_bdelay_slot = true;
-                } else {
-                    DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
-                            "after delay slot [sn:%i]\n", tid, squashed_inst+1);
-                    bdelay_done_seq_num = squashed_inst + 1;
-                    squash_bdelay_slot = false;
-                }
-            } else {
-                bdelay_done_seq_num = squashed_inst;
-            }
+            InstSeqNum bdelay_done_seq_num = squashed_inst;
+            bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
+
+            if (!squash_bdelay_slot)
+                bdelay_done_seq_num++;
+
 #endif
 
             if (fromIEW->includeSquashInst[tid] == true) {
@@ -1116,7 +1101,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     // Update the commit rename map
     for (int i = 0; i < head_inst->numDestRegs(); i++) {
-        renameMap[tid]->setEntry(head_inst->destRegIdx(i),
+        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
                                  head_inst->renamedDestRegIdx(i));
     }
 
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index ba5260fe2..85db68576 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -481,18 +481,26 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
     toCommit->branchMispredict[tid] = true;
 
 #if ISA_HAS_DELAY_SLOT
-    bool branch_taken = inst->readNextNPC() !=
-        (inst->readNextPC() + sizeof(TheISA::MachInst));
+    bool branch_taken =
+        (inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) &&
+         inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst)));
+    DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
+            branch_taken ? "true": "false", inst->seqNum);
 
     toCommit->branchTaken[tid] = branch_taken;
 
-    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
-
-    if (inst->isCondDelaySlot() && branch_taken) {
+    bool squashDelaySlot =
+        (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
+    DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
+            squashDelaySlot ? "true": "false", inst->seqNum);
+    toCommit->squashDelaySlot[tid] = squashDelaySlot;
+    //If we're squashing the delay slot, we need to pick back up at NextPC.
+    //Otherwise, NextPC isn't being squashed, so we should pick back up at
+    //NextNPC.
+    if (squashDelaySlot)
         toCommit->nextPC[tid] = inst->readNextPC();
-    } else {
+    else
         toCommit->nextPC[tid] = inst->readNextNPC();
-    }
 #else
     toCommit->branchTaken[tid] = inst->readNextPC() !=
         (inst->readPC() + sizeof(TheISA::MachInst));