From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 18 Sep 2020 08:01:34 +0000 (+0100)
Subject: dev-arm: Implement GICv4.1 GICD_TYPER2 as RES0
X-Git-Tag: develop-gem5-snapshot~725
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2035ebfbba599c520645b505241508f78b9b0636;p=gem5.git

dev-arm: Implement GICv4.1 GICD_TYPER2 as RES0

If GICv4.1 is not implemented (our case) the register should be
treated as RES0

Change-Id: Ia60f6dce9741c34bf167805f60c3fc8bf0897510
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34875
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 27f404b2b..27fbe9c55 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -472,6 +472,9 @@ Gicv3Distributor::read(Addr addr, size_t size, bool is_secure_access)
         //return 0x43b; // ARM JEP106 code (r0p0 GIC-500)
         return 0;
 
+      case GICD_TYPER2: // Interrupt Controller Type Register 2
+        return 0; // RES0
+
       case GICD_STATUSR: // Error Reporting Status Register
         // Optional register, RAZ/WI
         return 0x0;
diff --git a/src/dev/arm/gic_v3_distributor.hh b/src/dev/arm/gic_v3_distributor.hh
index 99b65ed9a..5e17e2af0 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -65,6 +65,8 @@ class Gicv3Distributor : public Serializable
         GICD_TYPER = 0x0004,
         // Implementer Identification Register
         GICD_IIDR = 0x0008,
+        // Interrupt Controller Type Register 2
+        GICD_TYPER2 = 0x000C,
         // Error Reporting Status Register
         GICD_STATUSR = 0x0010,
         // Set Non-secure SPI Pending Register