From: Tobias Platen Date: Wed, 22 Sep 2021 18:00:58 +0000 (+0200) Subject: compldst_multi: add op_is_dcbz signal X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2050ba99f4b1227c7e6db29264b4d50cb0d70a28;p=soc.git compldst_multi: add op_is_dcbz signal --- diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index d95dfa52..06f8184f 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -20,6 +20,11 @@ Loads are activated when Go_Write[0] is enabled. The EA is computed, and (as long as there was no exception) the data comes out (at any time from the PortInterface), and is captured by the LDCompSTUnit. +TODO: dcbz, yes, that's going to be complicated, has to be done + with great care, to detect the case when dcbz is set + and *not* expect to read any data, just the address. + so, wait for RA but not RB. + Both LD and ST may request that the address be computed from summing operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with the immediate (from the opcode). @@ -275,6 +280,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # opcode decode op_is_ld = Signal(reset_less=True) op_is_st = Signal(reset_less=True) + op_is_dcbz = Signal(reset_less=True) # ALU/LD data output control alu_valid = Signal(reset_less=True) # ALU operands are valid @@ -321,10 +327,12 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # decode bits of operand (latched) oper_r = CompLDSTOpSubset(name="oper_r") # Dest register - comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST - comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD - comb += Display("compldst_multi: op_is_dcbz = %i", - (oper_r.insn_type == MicrOp.OP_DCBZ)) + comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST + comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD + comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ) # DCBZ + #uncomment if needed + #comb += Display("compldst_multi: op_is_dcbz = %i", + # (oper_r.insn_type == MicrOp.OP_DCBZ)) op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)