From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Jun 2021 12:13:33 +0000 (+0100)
Subject: add mapreduce "reverse gear" to PowerDecoder2. gets the reg num to
X-Git-Tag: xlen-bcd~428
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2058053cda3cc56af7e5cac42d3ef376c2e41ef9;p=openpower-isa.git

add mapreduce "reverse gear" to PowerDecoder2. gets the reg num to
swap direction instead of 0..VL-1 it is VL-1..0
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 495bd173..b81aa99b 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -123,8 +123,12 @@ class GPR(dict):
         """ XXX currently not used
         """
         rnum = self._get_regnum(attr)
+        # XXX TODO, this needs sorting! (1) reverse gear for mapreduce
+        # and (2) when doing element-width overrides.  used by
+        # GPR(x) or GPR[x] in pseudocode
         offs = self.svstate.srcstep
-        log("GPR getitem", attr, rnum, "srcoffs", offs)
+        log("GPR getitem TODO mapreduce reverse-gear", attr, rnum,
+             "srcoffs", offs)
         return self.regfile[rnum]
 
     def dump(self, printout=True):
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 3b854bdd..054de650 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1153,8 +1153,10 @@ class PowerDecode2(PowerDecodeSubset):
             comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
 
             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
+            vl = Signal.like(self.state.svstate.vl)
             srcstep = Signal.like(self.state.svstate.srcstep)
             dststep = Signal.like(self.state.svstate.dststep)
+            comb += vl.eq(self.state.svstate.vl)
             comb += srcstep.eq(self.state.svstate.srcstep)
             comb += dststep.eq(self.state.svstate.dststep)
 
@@ -1173,7 +1175,11 @@ class PowerDecode2(PowerDecodeSubset):
                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
                 with m.If(svdec.isvec):
                     step = dststep if out else srcstep
-                    comb += to_reg.data.eq(step+svdec.reg_out)
+                    # reverse gear goes the opposite way
+                    with m.If(self.rm_dec.reverse_gear):
+                        comb += to_reg.data.eq(step+svdec.reg_out)
+                    with m.Else():
+                        comb += to_reg.data.eq(svdec.reg_out+(vl-1-step))
                 with m.Else():
                     comb += to_reg.data.eq(svdec.reg_out)