From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Jan 2022 21:23:49 +0000 (+0000)
Subject: comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=205b54594eb4a8614c44fe0ddf7a8e59d7076da5;p=soc.git

comments
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index bbb655f0..4cd1c0ab 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -573,7 +573,7 @@ class DTLBUpdate(Elaboratable):
         # on a one-clock delay, hence the register
         r_tlb_way        = TLBRecord("r_tlb_way")
         with m.If(r_delay):
-            # on one clock delay, output the contents of the read port(s)
+            # on one clock delay, capture the contents of the read port(s)
             comb += self.tlb_way.tag.eq(rd_tagway.data)
             comb += self.tlb_way.pte.eq(rd_pteway.data)
             sync += r_tlb_way.tag.eq(rd_tagway.data)