From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 18:34:16 +0000 (+0100)
Subject: initialise L0 Memory from simulator memory
X-Git-Tag: div_pipeline~524
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=205f904a8bb01285707c6448961b86ce843ff7c4;p=soc.git

initialise L0 Memory from simulator memory
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index b32f43da..602a9984 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -146,6 +146,16 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
+                # initialise memory
+                if self.funit == Function.LDST:
+                    mem = l0.mem.mem
+                    memlist = []
+                    for i in range(mem.depth):
+                        memlist.append(sim.mem.ld(i*8, 8))
+                    mem.init = memlist
+                    print (mem, mem.depth, mem.width)
+                    print ("mem init", list(map(hex,memlist)))
+
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]