From: Anton Blanchard Date: Mon, 9 Dec 2019 05:12:37 +0000 (+1100) Subject: Add SPI configuration to Xilinx constraint files X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20674e0d65f5aef1e966bdd10cd8999da0f96f2b;p=microwatt.git Add SPI configuration to Xilinx constraint files Signed-off-by: Anton Blanchard --- diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc index 481d8e4..a635211 100644 --- a/fpga/arty_a7.xdc +++ b/fpga/arty_a7.xdc @@ -8,3 +8,7 @@ set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_ set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] diff --git a/fpga/cmod_a7-35.xdc b/fpga/cmod_a7-35.xdc index 5f4aab2..3492d54 100644 --- a/fpga/cmod_a7-35.xdc +++ b/fpga/cmod_a7-35.xdc @@ -6,3 +6,10 @@ set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_ set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]; + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc index 6fc09f3..239376f 100644 --- a/fpga/nexys-video.xdc +++ b/fpga/nexys-video.xdc @@ -8,3 +8,7 @@ set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc index 08e73e2..a572772 100644 --- a/fpga/nexys_a7.xdc +++ b/fpga/nexys_a7.xdc @@ -8,3 +8,7 @@ set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design]