From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Feb 2019 01:04:23 +0000 (-0800)
Subject: Fix stitching
X-Git-Tag: working-ls180~1237^2~338
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=206f11dca3210931c542fb010f525949f1246540;p=yosys.git

Fix stitching
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 65eafffd9..278251320 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -653,6 +653,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			design->select(module, cell);
 		}
 
+		// FIXME: Better way to clean out module contents?
+		module->connections_.clear();
+
 		for (auto conn : mapped_mod->connections()) {
 			if (!conn.first.is_fully_const()) {
 				auto chunks = conn.first.chunks();
@@ -660,7 +663,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					c.wire = module->wires_[remap_name(c.wire->name)];
 				conn.first = std::move(chunks);
 			}
-			if (!conn.second.is_fully_const() && conn.second.is_wire()) {
+			if (!conn.second.is_fully_const()) {
 				auto chunks = conn.second.chunks();
 				for (auto &c : chunks)
 					c.wire = module->wires_[remap_name(c.wire->name)];
@@ -698,9 +701,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		//		module->connect(conn);
 		//	}
 
-		// FIXME:
-		module->connections_.clear();
-
 		for (auto &it : mapped_mod->wires_) {
 			RTLIL::Wire *w = it.second;
 			if (!w->port_input && !w->port_output)