From: Zachary Snow Date: Thu, 30 Dec 2021 07:06:23 +0000 (-0700) Subject: fixup verilog doubleslash test X-Git-Tag: yosys-0.13~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=207af4196b588546344db80df6cb3f77df784aaf;p=yosys.git fixup verilog doubleslash test - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again --- diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore index 34da23437..96ebe20ba 100644 --- a/tests/verilog/.gitignore +++ b/tests/verilog/.gitignore @@ -3,3 +3,4 @@ /run-test.mk /const_arst.v /const_sr.v +/doubleslash.v diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys index 8a51f12c2..c41673ee5 100644 --- a/tests/verilog/doubleslash.ys +++ b/tests/verilog/doubleslash.ys @@ -17,3 +17,5 @@ proc opt -full write_verilog doubleslash.v +design -reset +read_verilog doubleslash.v