From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 31 Mar 2022 09:02:39 +0000 (+0100)
Subject: whitespace cleanup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=207b747850b1c435cb5f4d2ee16df5bc5c291300;p=ls2.git

whitespace cleanup
---

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 74237ff..6872e3d 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -82,7 +82,7 @@ int main(void) {
 	volatile uint32_t *qspi = (uint32_t*)0x10000000;
     // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
     // tmp = readl((unsigned long)&(qspi[0]));
-#if 0
+#if 1
     while (1) {
         // quick read
         tmp = readl((unsigned long)&(qspi[0x1000/4]));
diff --git a/qspi_model/README.txt b/qspi_model/README.txt
index 52f57f2..4ec1d36 100644
--- a/qspi_model/README.txt
+++ b/qspi_model/README.txt
@@ -7,3 +7,6 @@ https://media-www.micron.com/-/media/client/global/documents/products/sim-model/
 the micron n25q model contains the following copyright notice:
 Copyright 2013 Micron Technology, Inc. All rights reserved.
 (no license given, disclaimer noted)
+
+* download cyperss model:
+https://community.infineon.com/gfawx74859/attachments/gfawx74859/NonVolatileRAM/994/1/Cy15b104qs.zip
diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 3bba16d..fcb6ecb 100755
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -5,11 +5,13 @@ LIB_DIR=./src/ecp5u
 
 HYPERRAM_DIR=./hyperram_model/s27kl0641/model
 
+QSPI_DIR=./qspi_model/N25Q256A11E_VG15/
+
 # create the build_simsoc/top.il file with firmware baked-in
-python3 src/ls2.py isim ./coldboot/coldboot.bin
+#python3 src/ls2.py isim ./coldboot/coldboot.bin
 
 # do some voodoo magic to get icarus to be happy with the ilang file
-yosys simsoc.ys
+#yosys simsoc.ys
 
 # fix a bug in Lattice ECP5 models
 cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
@@ -25,8 +27,13 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
     ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v \
     ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v ${LIB_DIR}/OBZ.v \
 	${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v \
+	${LIB_DIR}/UDFDL5E_UDP_X.v \
+	${LIB_DIR}/OFS1P3DX.v \
+	${LIB_DIR}/IFS1P3DX.v \
     ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \
     DDRDLLA.v \
+        -I ${QSPI_DIR} -DN25Q128A13E \
+    ${QSPI_DIR}/code/N25Qxxx.v \
 	${LIB_DIR}/CLKDIVF.v
 vvp -n simsoc -fst-speed
diff --git a/simsoc.ys b/simsoc.ys
index bcdc85b..fcfb354 100644
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -16,6 +16,9 @@ read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
 read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
+read_verilog  ../tercel-qspi/tercel/phy.v 
+read_verilog  ../tercel-qspi/tercel/wishbone_spi_master.v
+
 read_verilog  ./external_core_top.v
 
 # stop yosys deleting stuff
diff --git a/src/ls2.py b/src/ls2.py
index 55a7b65..5895641 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -679,11 +679,12 @@ def build_platform(fpga, firmware):
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Override here to get FlashResource out of the way and enable Tercel
         # direct access to the SPI flash
-        spi_0_ios = [ Resource("spi_0", 0,
-                                        Subsignal("dq",   Pins("W2 V2 Y2 W1", dir="io")),
-                                        Subsignal("cs_n", Pins("R2", dir="o")),
-                                        Attrs(PULLMODE="NONE", DRIVE="4",
-                                        IO_TYPE="LVCMOS33")) ]
+        spi_0_ios = [
+            Resource("spi_0", 0,
+                     Subsignal("dq",   Pins("W2 V2 Y2 W1", dir="io")),
+                     Subsignal("cs_n", Pins("R2", dir="o")),
+                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+        ]
         platform.add_resources(spi_0_ios)
         spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"},
                                                   xdr={"dq":1, "cs_n":0})
diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
index 5ae219d..1940560 100644
--- a/src/simsoc_hyperram_tb.v
+++ b/src/simsoc_hyperram_tb.v
@@ -3,6 +3,8 @@
 
 `timescale 1 ns / 1 ns
 
+`include "include/DevParam.h"
+
 module simsoc_hyperram_tb;
   // GSR & PUR init requires for Lattice models
   GSR GSR_INST (
@@ -36,6 +38,12 @@ module simsoc_hyperram_tb;
     wire [7:0] io_dq;
     wire io_rwds;
 
+    // SPI
+    wire spi_clk;
+    wire spi_cs_n;
+    wire spi_rst_n;
+    wire [3:0] io_spi_dq;
+
 s27kl0641
     #(
     .TimingModel("S27KL0641DABHI000"))
@@ -54,6 +62,17 @@ s27kl0641
     .RESETNeg(o_resetn)
     );
 
+   N25Qxxx N25Qxxx
+     (
+      .S(spi_cs_n),
+      .C_(spi_clk),
+      .HOLD_DQ3(io_spi_dq[3]),
+      .DQ0(io_spi_dq[0]),
+      .DQ1(io_spi_dq[1]),
+      .Vcc(VCC_3V),
+      .Vpp_W_DQ2(io_spi_dq[2])
+      );
+
   // uart, LEDs, switches
   wire uart_tx ;
   reg uart_rx = 0;
@@ -81,6 +100,10 @@ s27kl0641
     .hyperram_0__rwds__io(io_rwds), 
     .hyperram_0__ck__io(o_clk), 
     .hyperram_0__dq__io(io_dq),
+    // Quad SPI
+    .spi_flash_4x_0__dq__io(io_spi_dq),
+    .spi_flash_4x_0__cs__io(spi_cs_n),
+
     // uart
     .uart_0__rx__io(uart_rx),
     .uart_0__tx__io(uart_tx),
@@ -123,6 +146,9 @@ s27kl0641
 
   initial
     begin
+      
+      spi_clk = top.spi0.spi_clk;
+
       // run for a set time period then exit
       #120000000;