From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 27 Sep 2022 16:53:00 +0000 (+0100)
Subject: add unpack predicated unit test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20809f740abcb1a412decd26b94691c83ce2222e;p=openpower-isa.git

add unpack predicated unit test
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py
index 2afc6fdc..b80ec5dc 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_pack.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py
@@ -206,6 +206,62 @@ class DecoderTestCase(FHDLTestCase):
                     print ("checking", hex(expected.value), "at", offs)
                     self.assertEqual(sim.gpr(8+offs), expected)
 
+    def test_svstep_unpack(self):
+        """tests unpack mode with predicate
+        """
+        lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1",
+                        "svstep 0, 14, 0",  # set src-pack
+                        "sv.ori/vec2/m=r3 *8, *16, 0", # copy with mask
+                        ])
+        lst = list(lst)
+
+        # SVSTATE
+        svstate = SVP64State()
+        #svstate.vl = 2 # VL
+        #svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        mask = 0b0101
+        initial_regs = [0xffffffff]*64
+        initial_regs[3] = mask
+        for i in range(8):
+            initial_regs[16+i] = i
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs, svstate=svstate)
+            print ("SVSTATE after", bin(sim.svstate.asint()))
+            print ("        vl", bin(sim.svstate.vl))
+            print ("        mvl", bin(sim.svstate.maxvl))
+            print ("    srcstep", bin(sim.svstate.srcstep))
+            print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate. vfirst))
+            sim.gpr.dump()
+            self.assertEqual(sim.svstate.vl, 4)
+            self.assertEqual(sim.svstate.maxvl, 4)
+            self.assertEqual(sim.svstate.srcstep, 0)
+            self.assertEqual(sim.svstate.dststep, 0)
+
+            # sigh, in sz=0 mode you end up skipping.  have to
+            # take that into account, extracting the expected values
+            to_expect = []
+            for j in range(2):
+                for i in range(4):
+                    offs = j*4+i
+                    skew = i*2+j
+                    if mask & (1<<(offs>>1)):
+                        to_expect.append(offs)
+
+            print ("expected", to_expect)
+            for j in range(2):
+                for i in range(4):
+                    offs = j*4+i
+                    skew = i*2+j
+                    if mask & (1<<(skew>>1)):
+                        expected = SelectableInt(to_expect.pop(0), 64)
+                    else:
+                        expected = SelectableInt(0xffffffff, 64)
+                    self.assertEqual(sim.gpr(8+skew), expected)
+
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None,
                               initial_sprs=None):