From: Matt Turner <mattst88@gmail.com>
Date: Fri, 25 Aug 2017 22:52:27 +0000 (-0700)
Subject: i965/fs: Don't apply POW/FDIV workaround on Gen10+
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2082c32950a9e3a4debc00b0d6da85404b923920;p=mesa.git

i965/fs: Don't apply POW/FDIV workaround on Gen10+

The documentation says it applies only to Gens 8 and 9.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
---

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 6489cc0d38f..2622a919173 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1639,6 +1639,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
        * and empirically this affects CHV as well.
        */
       if (devinfo->gen >= 8 &&
+          devinfo->gen <= 9 &&
           p->nr_insn > 1 &&
           brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
           brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&